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https://github.com/c64scene-ar/llvm-6502.git
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ae3a0be92e
integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72897 91177308-0d34-0410-b5e6-96231b3b80d8
33 lines
1.1 KiB
LLVM
33 lines
1.1 KiB
LLVM
; RUN: llvm-as < %s | llc -pre-RA-sched=default
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; RUN: llvm-as < %s | llc -pre-RA-sched=list-burr
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; RUN: llvm-as < %s | llc -pre-RA-sched=fast
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; PR859
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; The top-down schedulers are excluded here because they don't yet support
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; targets that use physreg defs.
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declare i32 @printf(i8*, i32, float)
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define i32 @testissue(i32 %i, float %x, float %y) {
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br label %bb1
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bb1: ; preds = %bb1, %0
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%x1 = fmul float %x, %y ; <float> [#uses=1]
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%y1 = fmul float %y, 7.500000e-01 ; <float> [#uses=1]
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%z1 = fadd float %x1, %y1 ; <float> [#uses=1]
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%x2 = fmul float %x, 5.000000e-01 ; <float> [#uses=1]
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%y2 = fmul float %y, 0x3FECCCCCC0000000 ; <float> [#uses=1]
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%z2 = fadd float %x2, %y2 ; <float> [#uses=1]
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%z3 = fadd float %z1, %z2 ; <float> [#uses=1]
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%i1 = shl i32 %i, 3 ; <i32> [#uses=1]
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%j1 = add i32 %i, 7 ; <i32> [#uses=1]
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%m1 = add i32 %i1, %j1 ; <i32> [#uses=2]
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%b = icmp sle i32 %m1, 6 ; <i1> [#uses=1]
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br i1 %b, label %bb1, label %bb2
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bb2: ; preds = %bb1
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%Msg = inttoptr i64 0 to i8* ; <i8*> [#uses=1]
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call i32 @printf( i8* %Msg, i32 %m1, float %z3 ) ; <i32>:1 [#uses=0]
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ret i32 0
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}
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