llvm-6502

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History

Matt Arsenault ec0a7cd15a R600/SI: Remove i1 pseudo VALU ops

Select i1 logical ops directly to 64-bit SALU instructions.
Vector i1 values are always really in SGPRs, with each
bit for each item in the wave. This saves about 4 instructions
when and/or/xoring any condition, and also helps write conditions
that need to be passed in vcc.

This should work correctly now that the SGPR live range
fixing pass works. More work is needed to eliminate the VReg_1
pseudo regclass and possibly the entire SILowerI1Copies pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223206 91177308-0d34-0410-b5e6-96231b3b80d8

2014-12-03 05:22:35 +00:00

AArch64

AArch64: strengthen Darwin ABI alignment assumptions

2014-12-02 23:53:43 +00:00

ARM

Emit Tag_ABI_FP_denormal correctly in fast-math mode.

2014-12-02 08:22:29 +00:00

CPP

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Generic

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Hexagon