Ahmed Bougacha ec35069525 [CodeGen] Add hook/combine to form vector extloads, enabled on X86. ... The combine that forms extloads used to be disabled on vector types, because "None of the supported targets knows how to perform load and sign extend on vectors in one instruction." That's not entirely true, since at least SSE4.1 X86 knows how to do those sextloads/zextloads (with PMOVS/ZX). But there are several aspects to getting this right. First, vector extloads are controlled by a profitability callback. For instance, on ARM, several instructions have folded extload forms, so it's not always beneficial to create an extload node (and trying to match extloads is a whole 'nother can of worms). The interesting optimization enables folding of s/zextloads to illegal (splittable) vector types, expanding them into smaller legal extloads. It's not ideal (it introduces some legalization-like behavior in the combine) but it's better than the obvious alternative: form illegal extloads, and later try to split them up. If you do that, you might generate extloads that can't be split up, but have a valid ext+load expansion. At vector-op legalization time, it's too late to generate this kind of code, so you end up forced to scalarize. It's better to just avoid creating egregiously illegal nodes. This optimization is enabled unconditionally on X86. Note that the splitting combine is happy with "custom" extloads. As is, this bypasses the actual custom lowering, and just unrolls the extload. But from what I've seen, this is still much better than the current custom lowering, which does some kind of unrolling at the end anyway (see for instance load_sext_4i8_to_4i64 on SSE2, and the added FIXME). Also note that the existing combine that forms extloads is now also enabled on legal vectors. This doesn't have a big effect on X86 (because sext+load is usually combined to sext_inreg+aextload). On ARM it fires on some rare occasions; that's for a separate commit. Differential Revision: http://reviews.llvm.org/D6904 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228325 91177308-0d34-0410-b5e6-96231b3b80d8		2015-02-05 18:31:02 +00:00
..
Analysis	Value soft float calls as more expensive in the inliner.	2015-02-05 02:09:33 +00:00
AsmParser	AsmParser: Split out LineField, NFC	2015-02-04 22:59:18 +00:00
Bitcode	IR: Initialize MDNode abbreviations en masse, NFC	2015-02-04 21:54:12 +00:00
CodeGen	[CodeGen] Add hook/combine to form vector extloads, enabled on X86.	2015-02-05 18:31:02 +00:00
DebugInfo
ExecutionEngine	[MC] Remove various unused MCAsmInfo parameters.	2015-02-05 00:58:51 +00:00
Fuzzer	[fuzzer] add flag prefer_small_during_initial_shuffle, be a bit more verbose	2015-02-04 23:42:42 +00:00
IR	Teach isDereferenceablePointer() to look through bitcast constant expressions.	2015-02-05 09:15:37 +00:00
IRReader
LineEditor
Linker
LTO	[LTO API] split lto_codegen_compile to lto_codegen_optimize and	2015-02-03 18:39:15 +00:00
MC	Try to fix the build in MCValue.cpp	2015-02-05 01:23:14 +00:00
Object
Option
ProfileData	InstrProf: Use a stable sort when reading coverage regions	2015-02-04 00:12:18 +00:00
Support	SpecialCaseList: Add support for parsing multiple input files.	2015-02-04 17:39:48 +00:00
TableGen
Target	[CodeGen] Add hook/combine to form vector extloads, enabled on X86.	2015-02-05 18:31:02 +00:00
Transforms	LowerSwitch: Use ConstantInt for CaseRange::{Low,High}	2015-02-05 16:58:10 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile