Colin LeMahieu ec51bc6f3a [Hexagon] Adding sub/and/or reg, imm forms ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223522 91177308-0d34-0410-b5e6-96231b3b80d8		2014-12-05 21:38:29 +00:00
..
AArch64	Condition codes AL and NV are invalid in the aliases that use	2014-06-10 13:11:35 +00:00
ARM	Add support for ARM modified-immediate assembly syntax.	2014-12-02 10:53:20 +00:00
Hexagon	[Hexagon] Adding sub/and/or reg, imm forms	2014-12-05 21:38:29 +00:00
Mips	The andi16, addiusp and jraddiusp micromips instructions were missing dedicated decoder methods in MipsDisassembler.cpp to properly decode immediate operands. These methods are added together with corresponding tests.	2014-12-01 11:12:04 +00:00
PowerPC	[PowerPC] Add asm support for cache-inhibited ld/st instructions	2014-11-30 10:15:56 +00:00
Sparc
SystemZ	[SystemZ] Add MC support for LEDBRA, LEXBRA and LDXBRA	2014-07-10 11:00:55 +00:00
X86	AVX-512: Fixed encoding of VPBROADCASTM and added SKX forms of this instruction	2014-10-26 09:52:24 +00:00
XCore