mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-30 05:29:47 +00:00
3185f9a2ea
on the size of the extraction and its position in the 64 bit word. This patch allows support of the dext transformations with mips64 direct object output. 0 <= msb < 32 0 <= lsb < 32 0 <= pos < 32 1 <= size <= 32 DINS The field is entirely contained in the right-most word of the doubleword 32 <= msb < 64 0 <= lsb < 32 0 <= pos < 32 2 <= size <= 64 DINSM The field straddles the words of the doubleword 32 <= msb < 64 32 <= lsb < 64 32 <= pos < 64 1 <= size <= 32 DINSU The field is entirely contained in the left-most word of the doubleword git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163010 91177308-0d34-0410-b5e6-96231b3b80d8
231 lines
8.0 KiB
C++
231 lines
8.0 KiB
C++
//===-- MipsMCInstLower.cpp - Convert Mips MachineInstr to MCInst ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains code to lower Mips MachineInstrs to their corresponding
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// MCInst records.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsMCInstLower.h"
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#include "MipsAsmPrinter.h"
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#include "MipsInstrInfo.h"
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#include "MCTargetDesc/MipsBaseInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/Target/Mangler.h"
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using namespace llvm;
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MipsMCInstLower::MipsMCInstLower(MipsAsmPrinter &asmprinter)
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: AsmPrinter(asmprinter) {}
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void MipsMCInstLower::Initialize(Mangler *M, MCContext *C) {
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Mang = M;
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Ctx = C;
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}
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MCOperand MipsMCInstLower::LowerSymbolOperand(const MachineOperand &MO,
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MachineOperandType MOTy,
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unsigned Offset) const {
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MCSymbolRefExpr::VariantKind Kind;
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const MCSymbol *Symbol;
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switch(MO.getTargetFlags()) {
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default: llvm_unreachable("Invalid target flag!");
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case MipsII::MO_NO_FLAG: Kind = MCSymbolRefExpr::VK_None; break;
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case MipsII::MO_GPREL: Kind = MCSymbolRefExpr::VK_Mips_GPREL; break;
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case MipsII::MO_GOT_CALL: Kind = MCSymbolRefExpr::VK_Mips_GOT_CALL; break;
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case MipsII::MO_GOT16: Kind = MCSymbolRefExpr::VK_Mips_GOT16; break;
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case MipsII::MO_GOT: Kind = MCSymbolRefExpr::VK_Mips_GOT; break;
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case MipsII::MO_ABS_HI: Kind = MCSymbolRefExpr::VK_Mips_ABS_HI; break;
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case MipsII::MO_ABS_LO: Kind = MCSymbolRefExpr::VK_Mips_ABS_LO; break;
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case MipsII::MO_TLSGD: Kind = MCSymbolRefExpr::VK_Mips_TLSGD; break;
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case MipsII::MO_TLSLDM: Kind = MCSymbolRefExpr::VK_Mips_TLSLDM; break;
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case MipsII::MO_DTPREL_HI: Kind = MCSymbolRefExpr::VK_Mips_DTPREL_HI; break;
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case MipsII::MO_DTPREL_LO: Kind = MCSymbolRefExpr::VK_Mips_DTPREL_LO; break;
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case MipsII::MO_GOTTPREL: Kind = MCSymbolRefExpr::VK_Mips_GOTTPREL; break;
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case MipsII::MO_TPREL_HI: Kind = MCSymbolRefExpr::VK_Mips_TPREL_HI; break;
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case MipsII::MO_TPREL_LO: Kind = MCSymbolRefExpr::VK_Mips_TPREL_LO; break;
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case MipsII::MO_GPOFF_HI: Kind = MCSymbolRefExpr::VK_Mips_GPOFF_HI; break;
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case MipsII::MO_GPOFF_LO: Kind = MCSymbolRefExpr::VK_Mips_GPOFF_LO; break;
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case MipsII::MO_GOT_DISP: Kind = MCSymbolRefExpr::VK_Mips_GOT_DISP; break;
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case MipsII::MO_GOT_PAGE: Kind = MCSymbolRefExpr::VK_Mips_GOT_PAGE; break;
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case MipsII::MO_GOT_OFST: Kind = MCSymbolRefExpr::VK_Mips_GOT_OFST; break;
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case MipsII::MO_HIGHER: Kind = MCSymbolRefExpr::VK_Mips_HIGHER; break;
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case MipsII::MO_HIGHEST: Kind = MCSymbolRefExpr::VK_Mips_HIGHEST; break;
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}
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switch (MOTy) {
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case MachineOperand::MO_MachineBasicBlock:
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Symbol = MO.getMBB()->getSymbol();
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break;
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case MachineOperand::MO_GlobalAddress:
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Symbol = Mang->getSymbol(MO.getGlobal());
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Offset += MO.getOffset();
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break;
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case MachineOperand::MO_BlockAddress:
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Symbol = AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress());
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Offset += MO.getOffset();
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break;
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case MachineOperand::MO_ExternalSymbol:
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Symbol = AsmPrinter.GetExternalSymbolSymbol(MO.getSymbolName());
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Offset += MO.getOffset();
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break;
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case MachineOperand::MO_JumpTableIndex:
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Symbol = AsmPrinter.GetJTISymbol(MO.getIndex());
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break;
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case MachineOperand::MO_ConstantPoolIndex:
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Symbol = AsmPrinter.GetCPISymbol(MO.getIndex());
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Offset += MO.getOffset();
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break;
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default:
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llvm_unreachable("<unknown operand type>");
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}
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const MCSymbolRefExpr *MCSym = MCSymbolRefExpr::Create(Symbol, Kind, *Ctx);
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if (!Offset)
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return MCOperand::CreateExpr(MCSym);
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// Assume offset is never negative.
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assert(Offset > 0);
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const MCConstantExpr *OffsetExpr = MCConstantExpr::Create(Offset, *Ctx);
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const MCBinaryExpr *Add = MCBinaryExpr::CreateAdd(MCSym, OffsetExpr, *Ctx);
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return MCOperand::CreateExpr(Add);
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}
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/*
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static void CreateMCInst(MCInst& Inst, unsigned Opc, const MCOperand &Opnd0,
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const MCOperand &Opnd1,
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const MCOperand &Opnd2 = MCOperand()) {
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Inst.setOpcode(Opc);
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Inst.addOperand(Opnd0);
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Inst.addOperand(Opnd1);
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if (Opnd2.isValid())
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Inst.addOperand(Opnd2);
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}
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*/
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MCOperand MipsMCInstLower::LowerOperand(const MachineOperand &MO,
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unsigned offset) const {
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MachineOperandType MOTy = MO.getType();
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switch (MOTy) {
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default: llvm_unreachable("unknown operand type");
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case MachineOperand::MO_Register:
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// Ignore all implicit register operands.
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if (MO.isImplicit()) break;
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return MCOperand::CreateReg(MO.getReg());
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case MachineOperand::MO_Immediate:
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return MCOperand::CreateImm(MO.getImm() + offset);
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case MachineOperand::MO_MachineBasicBlock:
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case MachineOperand::MO_GlobalAddress:
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case MachineOperand::MO_ExternalSymbol:
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case MachineOperand::MO_JumpTableIndex:
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case MachineOperand::MO_ConstantPoolIndex:
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case MachineOperand::MO_BlockAddress:
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return LowerSymbolOperand(MO, MOTy, offset);
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case MachineOperand::MO_RegisterMask:
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break;
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}
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return MCOperand();
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}
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void MipsMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
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OutMI.setOpcode(MI->getOpcode());
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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MCOperand MCOp = LowerOperand(MO);
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if (MCOp.isValid())
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OutMI.addOperand(MCOp);
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}
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}
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// If the D<shift> instruction has a shift amount that is greater
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// than 31 (checked in calling routine), lower it to a D<shift>32 instruction
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void MipsMCInstLower::LowerLargeShift(const MachineInstr *MI,
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MCInst& Inst,
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int64_t Shift) {
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// rt
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Inst.addOperand(LowerOperand(MI->getOperand(0)));
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// rd
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Inst.addOperand(LowerOperand(MI->getOperand(1)));
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// saminus32
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Inst.addOperand(MCOperand::CreateImm(Shift));
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switch (MI->getOpcode()) {
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default:
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// Calling function is not synchronized
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llvm_unreachable("Unexpected shift instruction");
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break;
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case Mips::DSLL:
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Inst.setOpcode(Mips::DSLL32);
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break;
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case Mips::DSRL:
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Inst.setOpcode(Mips::DSRL32);
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break;
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case Mips::DSRA:
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Inst.setOpcode(Mips::DSRA32);
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break;
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}
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}
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// Pick a DEXT or DINS instruction variant based on the pos and size operands
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void MipsMCInstLower::LowerDextDins(const MachineInstr *MI, MCInst& Inst) {
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int Opcode = MI->getOpcode();
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if (Opcode == Mips::DEXT)
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assert(MI->getNumOperands() == 4 &&
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"Invalid no. of machine operands for DEXT!");
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else // Only DEXT and DINS are possible
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assert(MI->getNumOperands() == 5 &&
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"Invalid no. of machine operands for DINS!");
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assert(MI->getOperand(2).isImm());
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int64_t pos = MI->getOperand(2).getImm();
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assert(MI->getOperand(3).isImm());
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int64_t size = MI->getOperand(3).getImm();
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// rt
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Inst.addOperand(LowerOperand(MI->getOperand(0)));
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// rs
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Inst.addOperand(LowerOperand(MI->getOperand(1)));
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if (size <= 32) {
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if ((pos < 32)) { // DEXT/DINS
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Inst.addOperand(MCOperand::CreateImm(pos));
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Inst.addOperand(MCOperand::CreateImm(size));
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Inst.setOpcode(Opcode);
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} else { // DEXTU/DINSU
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Inst.addOperand(MCOperand::CreateImm(pos - 32));
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Inst.addOperand(MCOperand::CreateImm(size));
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Inst.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTU : Mips::DINSU);
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}
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} else { // DEXTM/DINSM
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assert(pos < 32 && "DEXT/DINS cannot have both size and pos > 32");
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Inst.addOperand(MCOperand::CreateImm(pos));
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Inst.addOperand(MCOperand::CreateImm(size - 32));
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Inst.setOpcode(Mips::DEXTM);
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Inst.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTM : Mips::DINSM);
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}
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}
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