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7eedd07d5e
Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229695 91177308-0d34-0410-b5e6-96231b3b80d8
11 lines
496 B
ArmAsm
11 lines
496 B
ArmAsm
# Instructions that are valid for the current ISA but should be rejected by the assembler (e.g.
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# invalid set of operands or operand's restrictions not met).
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# RUN: not llvm-mc %s -triple=mips64-unknown-linux -mcpu=mips64r3 2>%t1
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# RUN: FileCheck %s < %t1 -check-prefix=ASM
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.text
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.set noreorder
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jalr.hb $31 # ASM: :[[@LINE]]:9: error: source and destination must be different
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jalr.hb $31, $31 # ASM: :[[@LINE]]:9: error: source and destination must be different
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