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225ca9cdd7
important. - Cleanup in the Subtarget info with addition of new features, not all support yet, but they allow the future inclusion of features easier. Among new features, we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit integer and float registers, allegrex vector FPU (VFPU), single float only support. - TargetMachine now detects allegrex core. - Added allegrex (Mips32r2) sext_inreg instructions. - *Added Float Point Instructions*, handling single float only, and aliased accesses for 32-bit FPUs. - Some cleanup in FP instruction formats and FP register classes. - Calling conventions improved to support mips 32-bit EABI. - Added Asm Printer support for fp cond codes. - Added support for sret copy to a return register. - EABI support added into LowerCALL and FORMAL_ARGS. - MipsFunctionInfo now keeps a virtual register per function to track the sret on function entry until function ret. - MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...), FP cond codes mapping and initial FP Branch Analysis. - Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond, FPCmp - MipsTargetLowering : handling different FP classes, Allegrex support, sret return copy, no homing location within EABI, non 32-bit stack objects arguments, and asm constraint for float. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
43 lines
1.5 KiB
C++
43 lines
1.5 KiB
C++
//===- MipsSubtarget.cpp - Mips Subtarget Information -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the Mips specific subclass of TargetSubtarget.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsSubtarget.h"
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#include "Mips.h"
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#include "MipsGenSubtarget.inc"
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#include "llvm/Module.h"
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using namespace llvm;
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MipsSubtarget::MipsSubtarget(const TargetMachine &TM, const Module &M,
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const std::string &FS, bool little) :
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MipsArchVersion(Mips1), MipsABI(O32), IsLittle(little), IsSingleFloat(false),
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IsFP64bit(false), IsGP64bit(false), HasAllegrexVFPU(false), IsAllegrex(false)
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{
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std::string CPU = "mips1";
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// Parse features string.
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ParseSubtargetFeatures(FS, CPU);
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// When only the target triple is specified and is
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// a allegrex target, set the features. We also match
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// big and little endian allegrex cores (dont really
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// know if a big one exists)
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const std::string& TT = M.getTargetTriple();
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if (TT.find("mipsallegrex") != std::string::npos) {
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MipsABI = EABI;
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IsSingleFloat = true;
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MipsArchVersion = Mips2;
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HasAllegrexVFPU = true; // Enables Allegrex Vector FPU (not supported yet)
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IsAllegrex = true;
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}
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}
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