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225ca9cdd7
important. - Cleanup in the Subtarget info with addition of new features, not all support yet, but they allow the future inclusion of features easier. Among new features, we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit integer and float registers, allegrex vector FPU (VFPU), single float only support. - TargetMachine now detects allegrex core. - Added allegrex (Mips32r2) sext_inreg instructions. - *Added Float Point Instructions*, handling single float only, and aliased accesses for 32-bit FPUs. - Some cleanup in FP instruction formats and FP register classes. - Calling conventions improved to support mips 32-bit EABI. - Added Asm Printer support for fp cond codes. - Added support for sret copy to a return register. - EABI support added into LowerCALL and FORMAL_ARGS. - MipsFunctionInfo now keeps a virtual register per function to track the sret on function entry until function ret. - MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...), FP cond codes mapping and initial FP Branch Analysis. - Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond, FPCmp - MipsTargetLowering : handling different FP classes, Allegrex support, sret return copy, no homing location within EABI, non 32-bit stack objects arguments, and asm constraint for float. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
95 lines
2.7 KiB
C++
95 lines
2.7 KiB
C++
//=====-- MipsSubtarget.h - Define Subtarget for the Mips -----*- C++ -*--====//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the Mips specific subclass of TargetSubtarget.
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//
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//===----------------------------------------------------------------------===//
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#ifndef MIPSSUBTARGET_H
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#define MIPSSUBTARGET_H
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#include "llvm/Target/TargetSubtarget.h"
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#include "llvm/Target/TargetMachine.h"
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#include <string>
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namespace llvm {
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class Module;
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class MipsSubtarget : public TargetSubtarget {
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protected:
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enum MipsArchEnum {
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Mips1, Mips2, Mips3, Mips4, Mips32, Mips32r2
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};
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enum MipsABIEnum {
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O32, EABI
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};
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// Mips architecture version
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MipsArchEnum MipsArchVersion;
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// Mips supported ABIs
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MipsABIEnum MipsABI;
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// IsLittle - The target is Little Endian
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bool IsLittle;
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// IsSingleFloat - The target only supports single precision float
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// point operations. This enable the target to use all 32 32-bit
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// float point registers instead of only using even ones.
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bool IsSingleFloat;
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// IsFP64bit - The target processor has 64-bit float point registers.
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bool IsFP64bit;
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// IsFP64bit - General-purpose registers are 64 bits wide
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bool IsGP64bit;
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// HasAllegrexVFPU - Allegrex processor has a vector float point unit.
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bool HasAllegrexVFPU;
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// IsAllegrex - The target processor is a Allegrex core.
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bool IsAllegrex;
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InstrItineraryData InstrItins;
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public:
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/// Only O32 and EABI supported right now.
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bool isABI_EABI() const { return MipsABI == EABI; }
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bool isABI_O32() const { return MipsABI == O32; }
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/// This constructor initializes the data members to match that
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/// of the specified module.
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MipsSubtarget(const TargetMachine &TM, const Module &M,
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const std::string &FS, bool little);
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/// ParseSubtargetFeatures - Parses features string setting specified
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/// subtarget options. Definition of function is auto generated by tblgen.
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void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
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bool hasMips2Ops() const { return MipsArchVersion >= Mips2; }
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bool isLittle() const { return IsLittle; }
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bool isFP64bit() const { return IsFP64bit; };
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bool isGP64bit() const { return IsGP64bit; };
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bool isGP32bit() const { return !IsGP64bit; };
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bool isSingleFloat() const { return IsSingleFloat; };
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bool isNotSingleFloat() const { return !IsSingleFloat; };
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bool hasAllegrexVFPU() const { return HasAllegrexVFPU; };
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bool isAllegrex() const { return IsAllegrex; };
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};
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} // End llvm namespace
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#endif
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