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It will surely be needed by heuristics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160027 91177308-0d34-0410-b5e6-96231b3b80d8
619 lines
21 KiB
C++
619 lines
21 KiB
C++
//===-- EarlyIfConversion.cpp - If-conversion on SSA form machine code ----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Early if-conversion is for out-of-order CPUs that don't have a lot of
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// predicable instructions. The goal is to eliminate conditional branches that
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// may mispredict.
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//
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// Instructions from both sides of the branch are executed specutatively, and a
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// cmov instruction selects the result.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "early-ifcvt"
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#include "llvm/Function.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/PostOrderIterator.h"
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#include "llvm/ADT/SetVector.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/SparseSet.h"
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#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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// Absolute maximum number of instructions allowed per speculated block.
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// This bypasses all other heuristics, so it should be set fairly high.
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static cl::opt<unsigned>
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BlockInstrLimit("early-ifcvt-limit", cl::init(30), cl::Hidden,
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cl::desc("Maximum number of instructions per speculated block."));
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// Stress testing mode - disable heuristics.
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static cl::opt<bool> Stress("stress-early-ifcvt", cl::Hidden,
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cl::desc("Turn all knobs to 11"));
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typedef SmallSetVector<MachineBasicBlock*, 8> BlockSetVector;
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//===----------------------------------------------------------------------===//
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// SSAIfConv
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//===----------------------------------------------------------------------===//
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//
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// The SSAIfConv class performs if-conversion on SSA form machine code after
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// determining if it is possible. The class contains no heuristics; external
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// code should be used to determine when if-conversion is a good idea.
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//
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// SSAIfConv can convert both triangles and diamonds:
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//
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// Triangle: Head Diamond: Head
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// | \ / \_
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// | \ / |
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// | [TF]BB FBB TBB
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// | / \ /
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// | / \ /
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// Tail Tail
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//
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// Instructions in the conditional blocks TBB and/or FBB are spliced into the
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// Head block, and phis in the Tail block are converted to select instructions.
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//
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namespace {
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class SSAIfConv {
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const TargetInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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MachineRegisterInfo *MRI;
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public:
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/// The block containing the conditional branch.
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MachineBasicBlock *Head;
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/// The block containing phis after the if-then-else.
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MachineBasicBlock *Tail;
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/// The 'true' conditional block as determined by AnalyzeBranch.
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MachineBasicBlock *TBB;
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/// The 'false' conditional block as determined by AnalyzeBranch.
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MachineBasicBlock *FBB;
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/// isTriangle - When there is no 'else' block, either TBB or FBB will be
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/// equal to Tail.
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bool isTriangle() const { return TBB == Tail || FBB == Tail; }
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/// Information about each phi in the Tail block.
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struct PHIInfo {
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MachineInstr *PHI;
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unsigned TReg, FReg;
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// Latencies from Cond+Branch, TReg, and FReg to DstReg.
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int CondCycles, TCycles, FCycles;
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PHIInfo(MachineInstr *phi)
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: PHI(phi), TReg(0), FReg(0), CondCycles(0), TCycles(0), FCycles(0) {}
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};
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SmallVector<PHIInfo, 8> PHIs;
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private:
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/// The branch condition determined by AnalyzeBranch.
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SmallVector<MachineOperand, 4> Cond;
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/// Instructions in Head that define values used by the conditional blocks.
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/// The hoisted instructions must be inserted after these instructions.
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SmallPtrSet<MachineInstr*, 8> InsertAfter;
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/// Register units clobbered by the conditional blocks.
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BitVector ClobberedRegUnits;
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// Scratch pad for findInsertionPoint.
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SparseSet<unsigned> LiveRegUnits;
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/// Insertion point in Head for speculatively executed instructions form TBB
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/// and FBB.
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MachineBasicBlock::iterator InsertionPoint;
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/// Return true if all non-terminator instructions in MBB can be safely
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/// speculated.
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bool canSpeculateInstrs(MachineBasicBlock *MBB);
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/// Find a valid insertion point in Head.
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bool findInsertionPoint();
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public:
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/// runOnMachineFunction - Initialize per-function data structures.
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void runOnMachineFunction(MachineFunction &MF) {
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TII = MF.getTarget().getInstrInfo();
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TRI = MF.getTarget().getRegisterInfo();
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MRI = &MF.getRegInfo();
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LiveRegUnits.clear();
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LiveRegUnits.setUniverse(TRI->getNumRegUnits());
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ClobberedRegUnits.clear();
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ClobberedRegUnits.resize(TRI->getNumRegUnits());
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}
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/// canConvertIf - If the sub-CFG headed by MBB can be if-converted,
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/// initialize the internal state, and return true.
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bool canConvertIf(MachineBasicBlock *MBB);
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/// convertIf - If-convert the last block passed to canConvertIf(), assuming
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/// it is possible. Add any erased blocks to RemovedBlocks.
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void convertIf(SmallVectorImpl<MachineBasicBlock*> &RemovedBlocks);
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};
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} // end anonymous namespace
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/// canSpeculateInstrs - Returns true if all the instructions in MBB can safely
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/// be speculated. The terminators are not considered.
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///
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/// If instructions use any values that are defined in the head basic block,
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/// the defining instructions are added to InsertAfter.
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///
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/// Any clobbered regunits are added to ClobberedRegUnits.
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///
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bool SSAIfConv::canSpeculateInstrs(MachineBasicBlock *MBB) {
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// Reject any live-in physregs. It's probably CPSR/EFLAGS, and very hard to
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// get right.
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if (!MBB->livein_empty()) {
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DEBUG(dbgs() << "BB#" << MBB->getNumber() << " has live-ins.\n");
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return false;
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}
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unsigned InstrCount = 0;
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// Check all instructions, except the terminators. It is assumed that
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// terminators never have side effects or define any used register values.
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for (MachineBasicBlock::iterator I = MBB->begin(),
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E = MBB->getFirstTerminator(); I != E; ++I) {
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if (I->isDebugValue())
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continue;
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if (++InstrCount > BlockInstrLimit && !Stress) {
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DEBUG(dbgs() << "BB#" << MBB->getNumber() << " has more than "
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<< BlockInstrLimit << " instructions.\n");
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return false;
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}
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// There shouldn't normally be any phis in a single-predecessor block.
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if (I->isPHI()) {
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DEBUG(dbgs() << "Can't hoist: " << *I);
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return false;
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}
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// Don't speculate loads. Note that it may be possible and desirable to
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// speculate GOT or constant pool loads that are guaranteed not to trap,
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// but we don't support that for now.
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if (I->mayLoad()) {
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DEBUG(dbgs() << "Won't speculate load: " << *I);
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return false;
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}
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// We never speculate stores, so an AA pointer isn't necessary.
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bool DontMoveAcrossStore = true;
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if (!I->isSafeToMove(TII, 0, DontMoveAcrossStore)) {
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DEBUG(dbgs() << "Can't speculate: " << *I);
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return false;
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}
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// Check for any dependencies on Head instructions.
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for (MIOperands MO(I); MO.isValid(); ++MO) {
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if (MO->isRegMask()) {
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DEBUG(dbgs() << "Won't speculate regmask: " << *I);
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return false;
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}
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if (!MO->isReg())
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continue;
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unsigned Reg = MO->getReg();
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// Remember clobbered regunits.
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if (MO->isDef() && TargetRegisterInfo::isPhysicalRegister(Reg))
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for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
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ClobberedRegUnits.set(*Units);
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if (!MO->readsReg() || !TargetRegisterInfo::isVirtualRegister(Reg))
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continue;
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MachineInstr *DefMI = MRI->getVRegDef(Reg);
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if (!DefMI || DefMI->getParent() != Head)
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continue;
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if (InsertAfter.insert(DefMI))
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DEBUG(dbgs() << "BB#" << MBB->getNumber() << " depends on " << *DefMI);
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if (DefMI->isTerminator()) {
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DEBUG(dbgs() << "Can't insert instructions below terminator.\n");
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return false;
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}
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}
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}
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return true;
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}
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/// Find an insertion point in Head for the speculated instructions. The
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/// insertion point must be:
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///
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/// 1. Before any terminators.
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/// 2. After any instructions in InsertAfter.
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/// 3. Not have any clobbered regunits live.
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///
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/// This function sets InsertionPoint and returns true when successful, it
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/// returns false if no valid insertion point could be found.
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///
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bool SSAIfConv::findInsertionPoint() {
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// Keep track of live regunits before the current position.
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// Only track RegUnits that are also in ClobberedRegUnits.
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LiveRegUnits.clear();
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SmallVector<unsigned, 8> Reads;
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MachineBasicBlock::iterator FirstTerm = Head->getFirstTerminator();
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MachineBasicBlock::iterator I = Head->end();
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MachineBasicBlock::iterator B = Head->begin();
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while (I != B) {
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--I;
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// Some of the conditional code depends in I.
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if (InsertAfter.count(I)) {
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DEBUG(dbgs() << "Can't insert code after " << *I);
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return false;
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}
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// Update live regunits.
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for (MIOperands MO(I); MO.isValid(); ++MO) {
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// We're ignoring regmask operands. That is conservatively correct.
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if (!MO->isReg())
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continue;
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unsigned Reg = MO->getReg();
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if (!TargetRegisterInfo::isPhysicalRegister(Reg))
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continue;
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// I clobbers Reg, so it isn't live before I.
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if (MO->isDef())
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for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
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LiveRegUnits.erase(*Units);
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// Unless I reads Reg.
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if (MO->readsReg())
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Reads.push_back(Reg);
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}
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// Anything read by I is live before I.
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while (!Reads.empty())
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for (MCRegUnitIterator Units(Reads.pop_back_val(), TRI); Units.isValid();
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++Units)
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if (ClobberedRegUnits.test(*Units))
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LiveRegUnits.insert(*Units);
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// We can't insert before a terminator.
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if (I != FirstTerm && I->isTerminator())
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continue;
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// Some of the clobbered registers are live before I, not a valid insertion
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// point.
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if (!LiveRegUnits.empty()) {
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DEBUG({
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dbgs() << "Would clobber";
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for (SparseSet<unsigned>::const_iterator
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i = LiveRegUnits.begin(), e = LiveRegUnits.end(); i != e; ++i)
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dbgs() << ' ' << PrintRegUnit(*i, TRI);
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dbgs() << " live before " << *I;
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});
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continue;
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}
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// This is a valid insertion point.
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InsertionPoint = I;
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DEBUG(dbgs() << "Can insert before " << *I);
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return true;
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}
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DEBUG(dbgs() << "No legal insertion point found.\n");
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return false;
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}
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/// canConvertIf - analyze the sub-cfg rooted in MBB, and return true if it is
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/// a potential candidate for if-conversion. Fill out the internal state.
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///
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bool SSAIfConv::canConvertIf(MachineBasicBlock *MBB) {
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Head = MBB;
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TBB = FBB = Tail = 0;
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if (Head->succ_size() != 2)
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return false;
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MachineBasicBlock *Succ0 = Head->succ_begin()[0];
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MachineBasicBlock *Succ1 = Head->succ_begin()[1];
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// Canonicalize so Succ0 has MBB as its single predecessor.
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if (Succ0->pred_size() != 1)
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std::swap(Succ0, Succ1);
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if (Succ0->pred_size() != 1 || Succ0->succ_size() != 1)
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return false;
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// We could support additional Tail predecessors by updating phis instead of
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// eliminating them. Let's see an example where it matters first.
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Tail = Succ0->succ_begin()[0];
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if (Tail->pred_size() != 2)
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return false;
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// This is not a triangle.
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if (Tail != Succ1) {
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// Check for a diamond. We won't deal with any critical edges.
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if (Succ1->pred_size() != 1 || Succ1->succ_size() != 1 ||
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Succ1->succ_begin()[0] != Tail)
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return false;
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DEBUG(dbgs() << "\nDiamond: BB#" << Head->getNumber()
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<< " -> BB#" << Succ0->getNumber()
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<< "/BB#" << Succ1->getNumber()
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<< " -> BB#" << Tail->getNumber() << '\n');
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// Live-in physregs are tricky to get right when speculating code.
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if (!Tail->livein_empty()) {
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DEBUG(dbgs() << "Tail has live-ins.\n");
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return false;
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}
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} else {
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DEBUG(dbgs() << "\nTriangle: BB#" << Head->getNumber()
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<< " -> BB#" << Succ0->getNumber()
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<< " -> BB#" << Tail->getNumber() << '\n');
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}
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// This is a triangle or a diamond.
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// If Tail doesn't have any phis, there must be side effects.
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if (Tail->empty() || !Tail->front().isPHI()) {
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DEBUG(dbgs() << "No phis in tail.\n");
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return false;
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}
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// The branch we're looking to eliminate must be analyzable.
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Cond.clear();
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if (TII->AnalyzeBranch(*Head, TBB, FBB, Cond)) {
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DEBUG(dbgs() << "Branch not analyzable.\n");
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return false;
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}
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// This is weird, probably some sort of degenerate CFG.
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if (!TBB) {
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DEBUG(dbgs() << "AnalyzeBranch didn't find conditional branch.\n");
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return false;
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}
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// AnalyzeBranch doesn't set FBB on a fall-through branch.
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// Make sure it is always set.
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FBB = TBB == Succ0 ? Succ1 : Succ0;
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// Any phis in the tail block must be convertible to selects.
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PHIs.clear();
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MachineBasicBlock *TPred = TBB == Tail ? Head : TBB;
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MachineBasicBlock *FPred = FBB == Tail ? Head : FBB;
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for (MachineBasicBlock::iterator I = Tail->begin(), E = Tail->end();
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I != E && I->isPHI(); ++I) {
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PHIs.push_back(&*I);
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PHIInfo &PI = PHIs.back();
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// Find PHI operands corresponding to TPred and FPred.
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for (unsigned i = 1; i != PI.PHI->getNumOperands(); i += 2) {
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if (PI.PHI->getOperand(i+1).getMBB() == TPred)
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PI.TReg = PI.PHI->getOperand(i).getReg();
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if (PI.PHI->getOperand(i+1).getMBB() == FPred)
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PI.FReg = PI.PHI->getOperand(i).getReg();
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}
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assert(TargetRegisterInfo::isVirtualRegister(PI.TReg) && "Bad PHI");
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assert(TargetRegisterInfo::isVirtualRegister(PI.FReg) && "Bad PHI");
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// Get target information.
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if (!TII->canInsertSelect(*Head, Cond, PI.TReg, PI.FReg,
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PI.CondCycles, PI.TCycles, PI.FCycles)) {
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DEBUG(dbgs() << "Can't convert: " << *PI.PHI);
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return false;
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}
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}
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// Check that the conditional instructions can be speculated.
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InsertAfter.clear();
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ClobberedRegUnits.reset();
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if (TBB != Tail && !canSpeculateInstrs(TBB))
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return false;
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if (FBB != Tail && !canSpeculateInstrs(FBB))
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return false;
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// Try to find a valid insertion point for the speculated instructions in the
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// head basic block.
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if (!findInsertionPoint())
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return false;
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return true;
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}
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/// convertIf - Execute the if conversion after canConvertIf has determined the
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/// feasibility.
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///
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/// Any basic blocks erased will be added to RemovedBlocks.
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///
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void SSAIfConv::convertIf(SmallVectorImpl<MachineBasicBlock*> &RemovedBlocks) {
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assert(Head && Tail && TBB && FBB && "Call canConvertIf first.");
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// Move all instructions into Head, except for the terminators.
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if (TBB != Tail)
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Head->splice(InsertionPoint, TBB, TBB->begin(), TBB->getFirstTerminator());
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if (FBB != Tail)
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Head->splice(InsertionPoint, FBB, FBB->begin(), FBB->getFirstTerminator());
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MachineBasicBlock::iterator FirstTerm = Head->getFirstTerminator();
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assert(FirstTerm != Head->end() && "No terminators");
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DebugLoc HeadDL = FirstTerm->getDebugLoc();
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// Convert all PHIs to select instructions inserted before FirstTerm.
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for (unsigned i = 0, e = PHIs.size(); i != e; ++i) {
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PHIInfo &PI = PHIs[i];
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DEBUG(dbgs() << "If-converting " << *PI.PHI);
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assert(PI.PHI->getNumOperands() == 5 && "Unexpected PHI operands.");
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unsigned DstReg = PI.PHI->getOperand(0).getReg();
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TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg, PI.FReg);
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DEBUG(dbgs() << " --> " << *llvm::prior(FirstTerm));
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PI.PHI->eraseFromParent();
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PI.PHI = 0;
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}
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// Fix up the CFG, temporarily leave Head without any successors.
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Head->removeSuccessor(TBB);
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Head->removeSuccessor(FBB);
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if (TBB != Tail)
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TBB->removeSuccessor(Tail);
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if (FBB != Tail)
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FBB->removeSuccessor(Tail);
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// Fix up Head's terminators.
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// It should become a single branch or a fallthrough.
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TII->RemoveBranch(*Head);
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// Erase the now empty conditional blocks. It is likely that Head can fall
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// through to Tail, and we can join the two blocks.
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if (TBB != Tail) {
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RemovedBlocks.push_back(TBB);
|
|
TBB->eraseFromParent();
|
|
}
|
|
if (FBB != Tail) {
|
|
RemovedBlocks.push_back(FBB);
|
|
FBB->eraseFromParent();
|
|
}
|
|
|
|
assert(Head->succ_empty() && "Additional head successors?");
|
|
if (Head->isLayoutSuccessor(Tail)) {
|
|
// Splice Tail onto the end of Head.
|
|
DEBUG(dbgs() << "Joining tail BB#" << Tail->getNumber()
|
|
<< " into head BB#" << Head->getNumber() << '\n');
|
|
Head->splice(Head->end(), Tail,
|
|
Tail->begin(), Tail->end());
|
|
Head->transferSuccessorsAndUpdatePHIs(Tail);
|
|
RemovedBlocks.push_back(Tail);
|
|
Tail->eraseFromParent();
|
|
} else {
|
|
// We need a branch to Tail, let code placement work it out later.
|
|
DEBUG(dbgs() << "Converting to unconditional branch.\n");
|
|
SmallVector<MachineOperand, 0> EmptyCond;
|
|
TII->InsertBranch(*Head, Tail, 0, EmptyCond, HeadDL);
|
|
Head->addSuccessor(Tail);
|
|
}
|
|
DEBUG(dbgs() << *Head);
|
|
}
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// EarlyIfConverter Pass
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
namespace {
|
|
class EarlyIfConverter : public MachineFunctionPass {
|
|
const TargetInstrInfo *TII;
|
|
const TargetRegisterInfo *TRI;
|
|
MachineRegisterInfo *MRI;
|
|
MachineDominatorTree *DomTree;
|
|
MachineLoopInfo *Loops;
|
|
SSAIfConv IfConv;
|
|
|
|
public:
|
|
static char ID;
|
|
EarlyIfConverter() : MachineFunctionPass(ID) {}
|
|
void getAnalysisUsage(AnalysisUsage &AU) const;
|
|
bool runOnMachineFunction(MachineFunction &MF);
|
|
|
|
private:
|
|
bool tryConvertIf(MachineBasicBlock*);
|
|
void updateDomTree(ArrayRef<MachineBasicBlock*> Removed);
|
|
void updateLoops(ArrayRef<MachineBasicBlock*> Removed);
|
|
};
|
|
} // end anonymous namespace
|
|
|
|
char EarlyIfConverter::ID = 0;
|
|
char &llvm::EarlyIfConverterID = EarlyIfConverter::ID;
|
|
|
|
INITIALIZE_PASS_BEGIN(EarlyIfConverter,
|
|
"early-ifcvt", "Early If Converter", false, false)
|
|
INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)
|
|
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
|
|
INITIALIZE_PASS_END(EarlyIfConverter,
|
|
"early-ifcvt", "Early If Converter", false, false)
|
|
|
|
void EarlyIfConverter::getAnalysisUsage(AnalysisUsage &AU) const {
|
|
AU.addRequired<MachineBranchProbabilityInfo>();
|
|
AU.addRequired<MachineDominatorTree>();
|
|
AU.addPreserved<MachineDominatorTree>();
|
|
AU.addRequired<MachineLoopInfo>();
|
|
AU.addPreserved<MachineLoopInfo>();
|
|
MachineFunctionPass::getAnalysisUsage(AU);
|
|
}
|
|
|
|
/// Update the dominator tree after if-conversion erased some blocks.
|
|
void EarlyIfConverter::updateDomTree(ArrayRef<MachineBasicBlock*> Removed) {
|
|
// convertIf can remove TBB, FBB, and Tail can be merged into Head.
|
|
// TBB and FBB should not dominate any blocks.
|
|
// Tail children should be transferred to Head.
|
|
MachineDomTreeNode *HeadNode = DomTree->getNode(IfConv.Head);
|
|
for (unsigned i = 0, e = Removed.size(); i != e; ++i) {
|
|
MachineDomTreeNode *Node = DomTree->getNode(Removed[i]);
|
|
assert(Node != HeadNode && "Cannot erase the head node");
|
|
while (Node->getNumChildren()) {
|
|
assert(Node->getBlock() == IfConv.Tail && "Unexpected children");
|
|
DomTree->changeImmediateDominator(Node->getChildren().back(), HeadNode);
|
|
}
|
|
DomTree->eraseNode(Removed[i]);
|
|
}
|
|
}
|
|
|
|
/// Update LoopInfo after if-conversion.
|
|
void EarlyIfConverter::updateLoops(ArrayRef<MachineBasicBlock*> Removed) {
|
|
if (!Loops)
|
|
return;
|
|
// If-conversion doesn't change loop structure, and it doesn't mess with back
|
|
// edges, so updating LoopInfo is simply removing the dead blocks.
|
|
for (unsigned i = 0, e = Removed.size(); i != e; ++i)
|
|
Loops->removeBlock(Removed[i]);
|
|
}
|
|
|
|
/// Attempt repeated if-conversion on MBB, return true if successful.
|
|
///
|
|
bool EarlyIfConverter::tryConvertIf(MachineBasicBlock *MBB) {
|
|
bool Changed = false;
|
|
while (IfConv.canConvertIf(MBB)) {
|
|
// If-convert MBB and update analyses.
|
|
SmallVector<MachineBasicBlock*, 4> RemovedBlocks;
|
|
IfConv.convertIf(RemovedBlocks);
|
|
Changed = true;
|
|
updateDomTree(RemovedBlocks);
|
|
updateLoops(RemovedBlocks);
|
|
}
|
|
return Changed;
|
|
}
|
|
|
|
bool EarlyIfConverter::runOnMachineFunction(MachineFunction &MF) {
|
|
DEBUG(dbgs() << "********** EARLY IF-CONVERSION **********\n"
|
|
<< "********** Function: "
|
|
<< ((Value*)MF.getFunction())->getName() << '\n');
|
|
TII = MF.getTarget().getInstrInfo();
|
|
TRI = MF.getTarget().getRegisterInfo();
|
|
MRI = &MF.getRegInfo();
|
|
DomTree = &getAnalysis<MachineDominatorTree>();
|
|
Loops = getAnalysisIfAvailable<MachineLoopInfo>();
|
|
|
|
bool Changed = false;
|
|
IfConv.runOnMachineFunction(MF);
|
|
|
|
// Visit blocks in dominator tree post-order. The post-order enables nested
|
|
// if-conversion in a single pass. The tryConvertIf() function may erase
|
|
// blocks, but only blocks dominated by the head block. This makes it safe to
|
|
// update the dominator tree while the post-order iterator is still active.
|
|
for (po_iterator<MachineDominatorTree*>
|
|
I = po_begin(DomTree), E = po_end(DomTree); I != E; ++I)
|
|
if (tryConvertIf(I->getBlock()))
|
|
Changed = true;
|
|
|
|
MF.verify(this, "After early if-conversion");
|
|
return Changed;
|
|
}
|