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DAG scheduling during isel. Most new functionality is currently guarded by -enable-sched-cycles and -enable-sched-hazard. Added InstrItineraryData::IssueWidth field, currently derived from ARM itineraries, but could be initialized differently on other targets. Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is active, and if so how many cycles of state it holds. Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry into the scheduler's available queue. ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to get information about it's SUnits, provides RecedeCycle for bottom-up scheduling, correctly computes scoreboard depth, tracks IssueCount, and considers potential stall cycles when checking for hazards. ScheduleDAGRRList now models machine cycles and hazards (under flags). It tracks MinAvailableCycle, drives the hazard recognizer and priority queue's ready filter, manages a new PendingQueue, properly accounts for stall cycles, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122541 91177308-0d34-0410-b5e6-96231b3b80d8
266 lines
8.8 KiB
C++
266 lines
8.8 KiB
C++
//===---- ScheduleDAGList.cpp - Implement a list scheduler for isel DAG ---===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements a top-down list scheduler, using standard algorithms.
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// The basic approach uses a priority queue of available nodes to schedule.
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// One at a time, nodes are taken from the priority queue (thus in priority
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// order), checked for legality to schedule, and emitted if legal.
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//
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// Nodes may not be legal to schedule either due to structural hazards (e.g.
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// pipeline or resource constraints) or because an input to the instruction has
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// not completed execution.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "pre-RA-sched"
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#include "ScheduleDAGSDNodes.h"
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#include "llvm/CodeGen/LatencyPriorityQueue.h"
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#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
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#include "llvm/CodeGen/SchedulerRegistry.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/Statistic.h"
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#include <climits>
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using namespace llvm;
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STATISTIC(NumNoops , "Number of noops inserted");
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STATISTIC(NumStalls, "Number of pipeline stalls");
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static RegisterScheduler
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tdListDAGScheduler("list-td", "Top-down list scheduler",
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createTDListDAGScheduler);
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namespace {
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//===----------------------------------------------------------------------===//
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/// ScheduleDAGList - The actual list scheduler implementation. This supports
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/// top-down scheduling.
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///
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class ScheduleDAGList : public ScheduleDAGSDNodes {
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private:
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/// AvailableQueue - The priority queue to use for the available SUnits.
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///
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SchedulingPriorityQueue *AvailableQueue;
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/// PendingQueue - This contains all of the instructions whose operands have
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/// been issued, but their results are not ready yet (due to the latency of
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/// the operation). Once the operands become available, the instruction is
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/// added to the AvailableQueue.
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std::vector<SUnit*> PendingQueue;
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/// HazardRec - The hazard recognizer to use.
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ScheduleHazardRecognizer *HazardRec;
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public:
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ScheduleDAGList(MachineFunction &mf,
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SchedulingPriorityQueue *availqueue)
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: ScheduleDAGSDNodes(mf), AvailableQueue(availqueue) {
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const TargetMachine &tm = mf.getTarget();
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HazardRec = tm.getInstrInfo()->CreateTargetHazardRecognizer(&tm, this);
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}
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~ScheduleDAGList() {
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delete HazardRec;
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delete AvailableQueue;
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}
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void Schedule();
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private:
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void ReleaseSucc(SUnit *SU, const SDep &D);
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void ReleaseSuccessors(SUnit *SU);
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void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
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void ListScheduleTopDown();
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};
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} // end anonymous namespace
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/// Schedule - Schedule the DAG using list scheduling.
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void ScheduleDAGList::Schedule() {
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DEBUG(dbgs() << "********** List Scheduling **********\n");
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// Build the scheduling graph.
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BuildSchedGraph(NULL);
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AvailableQueue->initNodes(SUnits);
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ListScheduleTopDown();
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AvailableQueue->releaseState();
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}
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//===----------------------------------------------------------------------===//
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// Top-Down Scheduling
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//===----------------------------------------------------------------------===//
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/// ReleaseSucc - Decrement the NumPredsLeft count of a successor. Add it to
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/// the PendingQueue if the count reaches zero. Also update its cycle bound.
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void ScheduleDAGList::ReleaseSucc(SUnit *SU, const SDep &D) {
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SUnit *SuccSU = D.getSUnit();
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#ifndef NDEBUG
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if (SuccSU->NumPredsLeft == 0) {
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dbgs() << "*** Scheduling failed! ***\n";
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SuccSU->dump(this);
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dbgs() << " has been released too many times!\n";
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llvm_unreachable(0);
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}
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#endif
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--SuccSU->NumPredsLeft;
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SuccSU->setDepthToAtLeast(SU->getDepth() + D.getLatency());
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// If all the node's predecessors are scheduled, this node is ready
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// to be scheduled. Ignore the special ExitSU node.
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if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU)
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PendingQueue.push_back(SuccSU);
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}
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void ScheduleDAGList::ReleaseSuccessors(SUnit *SU) {
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// Top down: release successors.
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for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
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I != E; ++I) {
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assert(!I->isAssignedRegDep() &&
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"The list-td scheduler doesn't yet support physreg dependencies!");
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ReleaseSucc(SU, *I);
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}
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}
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/// ScheduleNodeTopDown - Add the node to the schedule. Decrement the pending
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/// count of its successors. If a successor pending count is zero, add it to
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/// the Available queue.
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void ScheduleDAGList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
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DEBUG(dbgs() << "*** Scheduling [" << CurCycle << "]: ");
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DEBUG(SU->dump(this));
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Sequence.push_back(SU);
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assert(CurCycle >= SU->getDepth() && "Node scheduled above its depth!");
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SU->setDepthToAtLeast(CurCycle);
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ReleaseSuccessors(SU);
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SU->isScheduled = true;
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AvailableQueue->ScheduledNode(SU);
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}
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/// ListScheduleTopDown - The main loop of list scheduling for top-down
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/// schedulers.
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void ScheduleDAGList::ListScheduleTopDown() {
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unsigned CurCycle = 0;
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// Release any successors of the special Entry node.
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ReleaseSuccessors(&EntrySU);
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// All leaves to Available queue.
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for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
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// It is available if it has no predecessors.
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if (SUnits[i].Preds.empty()) {
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AvailableQueue->push(&SUnits[i]);
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SUnits[i].isAvailable = true;
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}
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}
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// While Available queue is not empty, grab the node with the highest
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// priority. If it is not ready put it back. Schedule the node.
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std::vector<SUnit*> NotReady;
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Sequence.reserve(SUnits.size());
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while (!AvailableQueue->empty() || !PendingQueue.empty()) {
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// Check to see if any of the pending instructions are ready to issue. If
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// so, add them to the available queue.
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for (unsigned i = 0, e = PendingQueue.size(); i != e; ++i) {
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if (PendingQueue[i]->getDepth() == CurCycle) {
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AvailableQueue->push(PendingQueue[i]);
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PendingQueue[i]->isAvailable = true;
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PendingQueue[i] = PendingQueue.back();
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PendingQueue.pop_back();
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--i; --e;
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} else {
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assert(PendingQueue[i]->getDepth() > CurCycle && "Negative latency?");
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}
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}
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// If there are no instructions available, don't try to issue anything, and
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// don't advance the hazard recognizer.
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if (AvailableQueue->empty()) {
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++CurCycle;
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continue;
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}
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SUnit *FoundSUnit = 0;
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bool HasNoopHazards = false;
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while (!AvailableQueue->empty()) {
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SUnit *CurSUnit = AvailableQueue->pop();
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ScheduleHazardRecognizer::HazardType HT =
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HazardRec->getHazardType(CurSUnit, 0/*no stalls*/);
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if (HT == ScheduleHazardRecognizer::NoHazard) {
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FoundSUnit = CurSUnit;
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break;
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}
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// Remember if this is a noop hazard.
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HasNoopHazards |= HT == ScheduleHazardRecognizer::NoopHazard;
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NotReady.push_back(CurSUnit);
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}
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// Add the nodes that aren't ready back onto the available list.
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if (!NotReady.empty()) {
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AvailableQueue->push_all(NotReady);
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NotReady.clear();
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}
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// If we found a node to schedule, do it now.
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if (FoundSUnit) {
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ScheduleNodeTopDown(FoundSUnit, CurCycle);
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HazardRec->EmitInstruction(FoundSUnit);
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// If this is a pseudo-op node, we don't want to increment the current
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// cycle.
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if (FoundSUnit->Latency) // Don't increment CurCycle for pseudo-ops!
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++CurCycle;
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} else if (!HasNoopHazards) {
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// Otherwise, we have a pipeline stall, but no other problem, just advance
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// the current cycle and try again.
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DEBUG(dbgs() << "*** Advancing cycle, no work to do\n");
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HazardRec->AdvanceCycle();
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++NumStalls;
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++CurCycle;
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} else {
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// Otherwise, we have no instructions to issue and we have instructions
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// that will fault if we don't do this right. This is the case for
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// processors without pipeline interlocks and other cases.
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DEBUG(dbgs() << "*** Emitting noop\n");
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HazardRec->EmitNoop();
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Sequence.push_back(0); // NULL here means noop
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++NumNoops;
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++CurCycle;
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}
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}
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#ifndef NDEBUG
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VerifySchedule(/*isBottomUp=*/false);
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#endif
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}
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//===----------------------------------------------------------------------===//
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// Public Constructor Functions
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//===----------------------------------------------------------------------===//
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/// createTDListDAGScheduler - This creates a top-down list scheduler.
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ScheduleDAGSDNodes *
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llvm::createTDListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
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return new ScheduleDAGList(*IS->MF, new LatencyPriorityQueue());
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}
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