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f0c1388dd1
Aside from a few minor latency corrections, the major change here is a new hazard recognizer which focuses on better dispatch-group formation on the POWER7. As with the PPC970's hazard recognizer, the most important thing it does is avoid load-after-store hazards within the same dispatch group. It uses the POWER7's special dispatch-group-terminating nop instruction (instead of inserting multiple regular nop instructions). This new hazard recognizer makes use of the scheduling dependency graph itself, built using AA information, to robustly detect the possibility of load-after-store hazards. significant test-suite performance changes (the error bars are 99.5% confidence intervals based on 5 test-suite runs both with and without the change -- speedups are negative): speedups: MultiSource/Benchmarks/FreeBench/pcompress2/pcompress2 -0.55171% +/- 0.333168% MultiSource/Benchmarks/TSVC/CrossingThresholds-dbl/CrossingThresholds-dbl -17.5576% +/- 14.598% MultiSource/Benchmarks/TSVC/Reductions-dbl/Reductions-dbl -29.5708% +/- 7.09058% MultiSource/Benchmarks/TSVC/Reductions-flt/Reductions-flt -34.9471% +/- 11.4391% SingleSource/Benchmarks/BenchmarkGame/puzzle -25.1347% +/- 11.0104% SingleSource/Benchmarks/Misc/flops-8 -17.7297% +/- 9.79061% SingleSource/Benchmarks/Shootout-C++/ary3 -35.5018% +/- 23.9458% SingleSource/Regression/C/uint64_to_float -56.3165% +/- 25.4234% SingleSource/UnitTests/Vectorizer/gcc-loops -18.5309% +/- 6.8496% regressions: MultiSource/Benchmarks/ASCI_Purple/SMG2000/smg2000 18.351% +/- 12.156% SingleSource/Benchmarks/Shootout-C++/methcall 27.3086% +/- 14.4733% git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197099 91177308-0d34-0410-b5e6-96231b3b80d8
394 lines
22 KiB
TableGen
394 lines
22 KiB
TableGen
//===-- PPCScheduleP7.td - PPC P7 Scheduling Definitions ---*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the itinerary class data for the POWER7 processor.
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//
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//===----------------------------------------------------------------------===//
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// Primary reference:
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// IBM POWER7 multicore server processor
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// B. Sinharoy, et al.
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// IBM J. Res. & Dev. (55) 3. May/June 2011.
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// Scheduling for the P7 involves tracking two types of resources:
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// 1. The dispatch bundle slots
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// 2. The functional unit resources
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// Dispatch units:
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def P7_DU1 : FuncUnit;
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def P7_DU2 : FuncUnit;
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def P7_DU3 : FuncUnit;
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def P7_DU4 : FuncUnit;
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def P7_DU5 : FuncUnit;
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def P7_DU6 : FuncUnit;
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def P7_LS1 : FuncUnit; // Load/Store pipeline 1
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def P7_LS2 : FuncUnit; // Load/Store pipeline 2
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def P7_FX1 : FuncUnit; // FX pipeline 1
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def P7_FX2 : FuncUnit; // FX pipeline 2
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// VS pipeline 1 (vector integer ops. always here)
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def P7_VS1 : FuncUnit; // VS pipeline 1
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// VS pipeline 2 (128-bit stores and perms. here)
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def P7_VS2 : FuncUnit; // VS pipeline 2
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def P7_CRU : FuncUnit; // CR unit (CR logicals and move-from-SPRs)
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def P7_BRU : FuncUnit; // BR unit
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// Notes:
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// Each LSU pipeline can also execute FX add and logical instructions.
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// Each LSU pipeline can complete a load or store in one cycle.
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//
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// Each store is broken into two parts, AGEN goes to the LSU while a
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// "data steering" op. goes to the FXU or VSU.
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//
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// FX loads have a two cycle load-to-use latency (so one "bubble" cycle).
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// VSU loads have a three cycle load-to-use latency (so two "bubble" cycle).
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//
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// Frequent FX ops. take only one cycle and results can be used again in the
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// next cycle (there is a self-bypass). Getting results from the other FX
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// pipeline takes an additional cycle.
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//
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// The VSU XS is similar to the POWER6, but with a pipeline length of 2 cycles
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// (instead of 3 cycles on the POWER6). VSU XS handles vector FX-style ops.
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// Dispatch of an instruction to VS1 that uses four single prec. inputs
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// (either to a float or XC op). prevents dispatch in that cycle to VS2 of any
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// floating point instruction.
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//
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// The VSU PM is similar to the POWER6, but with a pipeline length of 3 cycles
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// (instead of 4 cycles on the POWER6). vsel is handled by the PM pipeline
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// (unlike on the POWER6).
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//
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// FMA from the VSUs can forward results in 6 cycles. VS1 XS and vector FP
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// share the same write-back, and have a 5-cycle latency difference, so the
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// IFU/IDU will not dispatch an XS instructon 5 cycles after a vector FP
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// op. has been dispatched to VS1.
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//
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// Three cycles after an L1 cache hit, a dependent VSU instruction can issue.
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//
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// Instruction dispatch groups have (at most) four non-branch instructions, and
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// two branches. Unlike on the POWER4/5, a branch does not automatically
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// end the dispatch group, but a second branch must be the last in the group.
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def P7Itineraries : ProcessorItineraries<
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[P7_DU1, P7_DU2, P7_DU3, P7_DU4, P7_DU5, P7_DU6,
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P7_LS1, P7_LS2, P7_FX1, P7_FX2, P7_VS1, P7_VS2, P7_CRU, P7_BRU], [], [
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InstrItinData<IIC_IntSimple , [InstrStage<1, [P7_DU1, P7_DU2,
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P7_DU3, P7_DU4], 0>,
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InstrStage<1, [P7_FX1, P7_FX2,
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P7_LS1, P7_LS2]>],
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[1, 1, 1]>,
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InstrItinData<IIC_IntGeneral , [InstrStage<1, [P7_DU1, P7_DU2,
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P7_DU3, P7_DU4], 0>,
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InstrStage<1, [P7_FX1, P7_FX2]>],
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[1, 1, 1]>,
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InstrItinData<IIC_IntCompare , [InstrStage<1, [P7_DU1, P7_DU2,
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P7_DU3, P7_DU4], 0>,
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InstrStage<1, [P7_FX1, P7_FX2]>],
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[1, 1, 1]>,
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// FIXME: Add record-form itinerary data.
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InstrItinData<IIC_IntDivW , [InstrStage<1, [P7_DU1], 0>,
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InstrStage<1, [P7_DU2], 0>,
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InstrStage<36, [P7_FX1, P7_FX2]>],
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[36, 1, 1]>,
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InstrItinData<IIC_IntDivD , [InstrStage<1, [P7_DU1], 0>,
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InstrStage<1, [P7_DU2], 0>,
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InstrStage<68, [P7_FX1, P7_FX2]>],
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[68, 1, 1]>,
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InstrItinData<IIC_IntMulHW , [InstrStage<1, [P7_DU1, P7_DU2,
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P7_DU3, P7_DU4], 0>,
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InstrStage<1, [P7_FX1, P7_FX2]>],
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[4, 1, 1]>,
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InstrItinData<IIC_IntMulHWU , [InstrStage<1, [P7_DU1, P7_DU2,
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P7_DU3, P7_DU4], 0>,
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InstrStage<1, [P7_FX1, P7_FX2]>],
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[4, 1, 1]>,
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InstrItinData<IIC_IntMulLI , [InstrStage<1, [P7_DU1, P7_DU2,
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P7_DU3, P7_DU4], 0>,
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InstrStage<1, [P7_FX1, P7_FX2]>],
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[4, 1, 1]>,
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InstrItinData<IIC_IntRotate , [InstrStage<1, [P7_DU1, P7_DU2,
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P7_DU3, P7_DU4], 0>,
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InstrStage<1, [P7_FX1, P7_FX2]>],
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[1, 1, 1]>,
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InstrItinData<IIC_IntRotateD , [InstrStage<1, [P7_DU1, P7_DU2,
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P7_DU3, P7_DU4], 0>,
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InstrStage<1, [P7_FX1, P7_FX2]>],
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[1, 1, 1]>,
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InstrItinData<IIC_IntShift , [InstrStage<1, [P7_DU1, P7_DU2,
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P7_DU3, P7_DU4], 0>,
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InstrStage<1, [P7_FX1, P7_FX2]>],
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[1, 1, 1]>,
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InstrItinData<IIC_IntTrapW , [InstrStage<1, [P7_DU1, P7_DU2,
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P7_DU3, P7_DU4], 0>,
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InstrStage<1, [P7_FX1, P7_FX2]>],
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[1, 1]>,
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InstrItinData<IIC_IntTrapD , [InstrStage<1, [P7_DU1, P7_DU2,
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P7_DU3, P7_DU4], 0>,
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InstrStage<1, [P7_FX1, P7_FX2]>],
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[1, 1]>,
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InstrItinData<IIC_BrB , [InstrStage<1, [P7_DU5, P7_DU6], 0>,
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InstrStage<1, [P7_BRU]>],
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[3, 1, 1]>,
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InstrItinData<IIC_BrCR , [InstrStage<1, [P7_DU5, P7_DU6], 0>,
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InstrStage<1, [P7_BRU]>],
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[3, 1, 1]>,
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InstrItinData<IIC_BrMCR , [InstrStage<1, [P7_DU5, P7_DU6], 0>,
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InstrStage<1, [P7_BRU]>],
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[3, 1, 1]>,
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InstrItinData<IIC_BrMCRX , [InstrStage<1, [P7_DU5, P7_DU6], 0>,
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InstrStage<1, [P7_BRU]>],
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[3, 1, 1]>,
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InstrItinData<IIC_LdStLoad , [InstrStage<1, [P7_DU1, P7_DU2,
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P7_DU3, P7_DU4], 0>,
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InstrStage<1, [P7_LS1, P7_LS2]>],
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[2, 1, 1]>,
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InstrItinData<IIC_LdStLoadUpd , [InstrStage<1, [P7_DU1], 0>,
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InstrStage<1, [P7_DU2], 0>,
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InstrStage<1, [P7_LS1, P7_LS2], 0>,
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InstrStage<1, [P7_FX1, P7_FX2]>],
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[2, 2, 1, 1]>,
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InstrItinData<IIC_LdStLoadUpdX, [InstrStage<1, [P7_DU1], 0>,
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InstrStage<1, [P7_DU2], 0>,
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InstrStage<1, [P7_DU3], 0>,
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InstrStage<1, [P7_DU4], 0>,
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InstrStage<1, [P7_FX1, P7_FX2]>,
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InstrStage<1, [P7_LS1, P7_LS2], 0>,
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InstrStage<1, [P7_FX1, P7_FX2]>],
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[3, 3, 1, 1]>,
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InstrItinData<IIC_LdStLD , [InstrStage<1, [P7_DU1, P7_DU2,
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P7_DU3, P7_DU4], 0>,
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InstrStage<1, [P7_LS1, P7_LS2]>],
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[2, 1, 1]>,
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InstrItinData<IIC_LdStLDU , [InstrStage<1, [P7_DU1], 0>,
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InstrStage<1, [P7_DU2], 0>,
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InstrStage<1, [P7_LS1, P7_LS2], 0>,
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InstrStage<1, [P7_FX1, P7_FX2]>],
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[2, 2, 1, 1]>,
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InstrItinData<IIC_LdStLDUX , [InstrStage<1, [P7_DU1], 0>,
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InstrStage<1, [P7_DU2], 0>,
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InstrStage<1, [P7_DU3], 0>,
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InstrStage<1, [P7_DU4], 0>,
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InstrStage<1, [P7_FX1, P7_FX2]>,
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InstrStage<1, [P7_LS1, P7_LS2], 0>,
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InstrStage<1, [P7_FX1, P7_FX2]>],
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[3, 3, 1, 1]>,
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InstrItinData<IIC_LdStLFD , [InstrStage<1, [P7_DU1, P7_DU2,
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P7_DU3, P7_DU4], 0>,
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InstrStage<1, [P7_LS1, P7_LS2]>],
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[3, 1, 1]>,
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InstrItinData<IIC_LdStLVecX , [InstrStage<1, [P7_DU1, P7_DU2,
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P7_DU3, P7_DU4], 0>,
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InstrStage<1, [P7_LS1, P7_LS2]>],
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[3, 1, 1]>,
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InstrItinData<IIC_LdStLFDU , [InstrStage<1, [P7_DU1], 0>,
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InstrStage<1, [P7_DU2], 0>,
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InstrStage<1, [P7_LS1, P7_LS2], 0>,
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InstrStage<1, [P7_FX1, P7_FX2]>],
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[3, 3, 1, 1]>,
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InstrItinData<IIC_LdStLFDUX , [InstrStage<1, [P7_DU1], 0>,
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InstrStage<1, [P7_DU2], 0>,
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InstrStage<1, [P7_LS1, P7_LS2], 0>,
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InstrStage<1, [P7_FX1, P7_FX2]>],
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[3, 3, 1, 1]>,
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InstrItinData<IIC_LdStLHA , [InstrStage<1, [P7_DU1], 0>,
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InstrStage<1, [P7_DU2], 0>,
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InstrStage<1, [P7_LS1, P7_LS2]>,
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InstrStage<1, [P7_FX1, P7_FX2]>],
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[3, 1, 1]>,
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InstrItinData<IIC_LdStLHAU , [InstrStage<1, [P7_DU1], 0>,
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InstrStage<1, [P7_DU2], 0>,
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InstrStage<1, [P7_LS1, P7_LS2], 0>,
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InstrStage<1, [P7_FX1, P7_FX2]>,
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InstrStage<1, [P7_FX1, P7_FX2]>],
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[4, 4, 1, 1]>,
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InstrItinData<IIC_LdStLHAUX , [InstrStage<1, [P7_DU1], 0>,
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InstrStage<1, [P7_DU2], 0>,
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InstrStage<1, [P7_DU3], 0>,
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InstrStage<1, [P7_DU4], 0>,
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InstrStage<1, [P7_FX1, P7_FX2]>,
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InstrStage<1, [P7_LS1, P7_LS2], 0>,
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InstrStage<1, [P7_FX1, P7_FX2]>,
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InstrStage<1, [P7_FX1, P7_FX2]>],
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[4, 4, 1, 1]>,
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InstrItinData<IIC_LdStLWA , [InstrStage<1, [P7_DU1], 0>,
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InstrStage<1, [P7_DU2], 0>,
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InstrStage<1, [P7_LS1, P7_LS2]>,
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InstrStage<1, [P7_FX1, P7_FX2]>],
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[3, 1, 1]>,
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InstrItinData<IIC_LdStLWARX, [InstrStage<1, [P7_DU1], 0>,
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InstrStage<1, [P7_DU2], 0>,
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InstrStage<1, [P7_DU3], 0>,
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InstrStage<1, [P7_DU4], 0>,
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InstrStage<1, [P7_LS1, P7_LS2]>],
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[3, 1, 1]>,
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InstrItinData<IIC_LdStLDARX, [InstrStage<1, [P7_DU1], 0>,
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InstrStage<1, [P7_DU2], 0>,
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InstrStage<1, [P7_DU3], 0>,
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InstrStage<1, [P7_DU4], 0>,
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InstrStage<1, [P7_LS1, P7_LS2]>],
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[3, 1, 1]>,
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InstrItinData<IIC_LdStLMW , [InstrStage<1, [P7_DU1, P7_DU2,
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P7_DU3, P7_DU4], 0>,
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InstrStage<1, [P7_LS1, P7_LS2]>],
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[2, 1, 1]>,
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InstrItinData<IIC_LdStStore , [InstrStage<1, [P7_DU1, P7_DU2,
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P7_DU3, P7_DU4], 0>,
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InstrStage<1, [P7_LS1, P7_LS2], 0>,
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InstrStage<1, [P7_FX1, P7_FX2]>],
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[1, 1, 1]>,
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InstrItinData<IIC_LdStSTD , [InstrStage<1, [P7_DU1, P7_DU2,
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P7_DU3, P7_DU4], 0>,
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InstrStage<1, [P7_LS1, P7_LS2], 0>,
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InstrStage<1, [P7_FX1, P7_FX2]>],
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[1, 1, 1]>,
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InstrItinData<IIC_LdStSTDU , [InstrStage<1, [P7_DU1], 0>,
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InstrStage<1, [P7_DU2], 0>,
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InstrStage<1, [P7_LS1, P7_LS2], 0>,
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InstrStage<1, [P7_FX1, P7_FX2]>,
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InstrStage<1, [P7_FX1, P7_FX2]>],
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[2, 1, 1, 1]>,
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InstrItinData<IIC_LdStSTDUX , [InstrStage<1, [P7_DU1], 0>,
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InstrStage<1, [P7_DU2], 0>,
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InstrStage<1, [P7_DU3], 0>,
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InstrStage<1, [P7_DU4], 0>,
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InstrStage<1, [P7_LS1, P7_LS2], 0>,
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InstrStage<1, [P7_FX1, P7_FX2]>,
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InstrStage<1, [P7_FX1, P7_FX2]>],
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[2, 1, 1, 1]>,
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InstrItinData<IIC_LdStSTFD , [InstrStage<1, [P7_DU1, P7_DU2,
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P7_DU3, P7_DU4], 0>,
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InstrStage<1, [P7_LS1, P7_LS2], 0>,
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InstrStage<1, [P7_VS1, P7_VS2]>],
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[1, 1, 1]>,
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InstrItinData<IIC_LdStSTFDU , [InstrStage<1, [P7_DU1], 0>,
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InstrStage<1, [P7_DU2], 0>,
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InstrStage<1, [P7_LS1, P7_LS2], 0>,
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InstrStage<1, [P7_FX1, P7_FX2], 0>,
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InstrStage<1, [P7_VS1, P7_VS2]>],
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[2, 1, 1, 1]>,
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InstrItinData<IIC_LdStSTVEBX , [InstrStage<1, [P7_DU1, P7_DU2,
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P7_DU3, P7_DU4], 0>,
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InstrStage<1, [P7_LS1, P7_LS2], 0>,
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InstrStage<1, [P7_VS2]>],
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[1, 1, 1]>,
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InstrItinData<IIC_LdStSTDCX , [InstrStage<1, [P7_DU1], 0>,
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InstrStage<1, [P7_DU2], 0>,
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InstrStage<1, [P7_DU3], 0>,
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InstrStage<1, [P7_DU4], 0>,
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InstrStage<1, [P7_LS1, P7_LS2]>],
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[1, 1, 1]>,
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InstrItinData<IIC_LdStSTWCX , [InstrStage<1, [P7_DU1], 0>,
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InstrStage<1, [P7_DU2], 0>,
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InstrStage<1, [P7_DU3], 0>,
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InstrStage<1, [P7_DU4], 0>,
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InstrStage<1, [P7_LS1, P7_LS2]>],
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[1, 1, 1]>,
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InstrItinData<IIC_BrMCRX , [InstrStage<1, [P7_DU1], 0>,
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InstrStage<1, [P7_DU2], 0>,
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InstrStage<1, [P7_DU3], 0>,
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InstrStage<1, [P7_DU4], 0>,
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InstrStage<1, [P7_CRU]>,
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InstrStage<1, [P7_FX1, P7_FX2]>],
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[3, 1]>, // mtcr
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InstrItinData<IIC_SprMFCR , [InstrStage<1, [P7_DU1], 0>,
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InstrStage<1, [P7_CRU]>],
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[6, 1]>,
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InstrItinData<IIC_SprMFCRF , [InstrStage<1, [P7_DU1], 0>,
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InstrStage<1, [P7_CRU]>],
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[3, 1]>,
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InstrItinData<IIC_SprMTSPR , [InstrStage<1, [P7_DU1], 0>,
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InstrStage<1, [P7_FX1]>],
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[4, 1]>, // mtctr
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InstrItinData<IIC_FPGeneral , [InstrStage<1, [P7_DU1, P7_DU2,
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P7_DU3, P7_DU4], 0>,
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InstrStage<1, [P7_VS1, P7_VS2]>],
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[5, 1, 1]>,
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InstrItinData<IIC_FPCompare , [InstrStage<1, [P7_DU1, P7_DU2,
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P7_DU3, P7_DU4], 0>,
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InstrStage<1, [P7_VS1, P7_VS2]>],
|
|
[8, 1, 1]>,
|
|
InstrItinData<IIC_FPDivD , [InstrStage<1, [P7_DU1, P7_DU2,
|
|
P7_DU3, P7_DU4], 0>,
|
|
InstrStage<1, [P7_VS1, P7_VS2]>],
|
|
[33, 1, 1]>,
|
|
InstrItinData<IIC_FPDivS , [InstrStage<1, [P7_DU1, P7_DU2,
|
|
P7_DU3, P7_DU4], 0>,
|
|
InstrStage<1, [P7_VS1, P7_VS2]>],
|
|
[27, 1, 1]>,
|
|
InstrItinData<IIC_FPSqrtD , [InstrStage<1, [P7_DU1, P7_DU2,
|
|
P7_DU3, P7_DU4], 0>,
|
|
InstrStage<1, [P7_VS1, P7_VS2]>],
|
|
[44, 1, 1]>,
|
|
InstrItinData<IIC_FPSqrtS , [InstrStage<1, [P7_DU1, P7_DU2,
|
|
P7_DU3, P7_DU4], 0>,
|
|
InstrStage<1, [P7_VS1, P7_VS2]>],
|
|
[32, 1, 1]>,
|
|
InstrItinData<IIC_FPFused , [InstrStage<1, [P7_DU1, P7_DU2,
|
|
P7_DU3, P7_DU4], 0>,
|
|
InstrStage<1, [P7_VS1, P7_VS2]>],
|
|
[5, 1, 1, 1]>,
|
|
InstrItinData<IIC_FPRes , [InstrStage<1, [P7_DU1, P7_DU2,
|
|
P7_DU3, P7_DU4], 0>,
|
|
InstrStage<1, [P7_VS1, P7_VS2]>],
|
|
[5, 1, 1]>,
|
|
InstrItinData<IIC_VecGeneral , [InstrStage<1, [P7_DU1, P7_DU2,
|
|
P7_DU3, P7_DU4], 0>,
|
|
InstrStage<1, [P7_VS1]>],
|
|
[2, 1, 1]>,
|
|
InstrItinData<IIC_VecVSL , [InstrStage<1, [P7_DU1, P7_DU2,
|
|
P7_DU3, P7_DU4], 0>,
|
|
InstrStage<1, [P7_VS1]>],
|
|
[2, 1, 1]>,
|
|
InstrItinData<IIC_VecVSR , [InstrStage<1, [P7_DU1, P7_DU2,
|
|
P7_DU3, P7_DU4], 0>,
|
|
InstrStage<1, [P7_VS1]>],
|
|
[2, 1, 1]>,
|
|
InstrItinData<IIC_VecFP , [InstrStage<1, [P7_DU1, P7_DU2,
|
|
P7_DU3, P7_DU4], 0>,
|
|
InstrStage<1, [P7_VS1, P7_VS2]>],
|
|
[6, 1, 1]>,
|
|
InstrItinData<IIC_VecFPCompare, [InstrStage<1, [P7_DU1, P7_DU2,
|
|
P7_DU3, P7_DU4], 0>,
|
|
InstrStage<1, [P7_VS1, P7_VS2]>],
|
|
[6, 1, 1]>,
|
|
InstrItinData<IIC_VecFPRound , [InstrStage<1, [P7_DU1, P7_DU2,
|
|
P7_DU3, P7_DU4], 0>,
|
|
InstrStage<1, [P7_VS1, P7_VS2]>],
|
|
[6, 1, 1]>,
|
|
InstrItinData<IIC_VecComplex , [InstrStage<1, [P7_DU1, P7_DU2,
|
|
P7_DU3, P7_DU4], 0>,
|
|
InstrStage<1, [P7_VS1]>],
|
|
[7, 1, 1]>,
|
|
InstrItinData<IIC_VecPerm , [InstrStage<1, [P7_DU1, P7_DU2,
|
|
P7_DU3, P7_DU4], 0>,
|
|
InstrStage<1, [P7_VS2]>],
|
|
[2, 1, 1]>
|
|
]>;
|
|
|
|
// ===---------------------------------------------------------------------===//
|
|
// P7 machine model for scheduling and other instruction cost heuristics.
|
|
|
|
def P7Model : SchedMachineModel {
|
|
let IssueWidth = 6; // 4 (non-branch) instructions are dispatched per cycle.
|
|
// Note that the dispatch bundle size is 6 (including
|
|
// branches), but the total internal issue bandwidth per
|
|
// cycle (from all queues) is 8.
|
|
|
|
let MinLatency = 0; // Out-of-order dispatch.
|
|
let LoadLatency = 3; // Optimistic load latency assuming bypass.
|
|
// This is overriden by OperandCycles if the
|
|
// Itineraries are queried instead.
|
|
let MispredictPenalty = 16;
|
|
|
|
let Itineraries = P7Itineraries;
|
|
}
|
|
|