llvm-6502/test/CodeGen
Matt Arsenault ed76ca720b R600/SI: Implement isLegalAddressingMode
The default assumes that a 16-bit signed offset is used.
LDS instruction use a 16-bit unsigned offset, so it wasn't
being used in some cases where it was assumed a negative offset
could be used.

More should be done here, but first isLegalAddressingMode needs
to gain an addressing mode argument. For now, copy most of the rest
of the default implementation with the immediate offset change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215732 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-15 17:17:07 +00:00
..
AArch64 [AArch64] Narrow arguments passed in wrong position on the stack in 2014-08-15 14:29:57 +00:00
ARM
CPP
Generic
Hexagon
Inputs
Mips
MSP430
NVPTX
PowerPC [PPC64] Add test case for r215685. 2014-08-15 13:51:57 +00:00
R600 R600/SI: Implement isLegalAddressingMode 2014-08-15 17:17:07 +00:00
SPARC
SystemZ
Thumb ARM: Fix and re-enable load/store optimizer for Thumb1. 2014-08-15 17:00:30 +00:00
Thumb2
X86
XCore