Tim Northover 5a02fc4b5f ARM: implement @llvm.readcyclecounter intrinsic ... This implements the @llvm.readcyclecounter intrinsic as the specific MRC instruction specified in the ARM manuals for CPUs with the Power Management extensions. Older CPUs had slightly different methods which may also have to be implemented eventually, but this should cover all v7 cases. rdar://problem/13939186 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182603 91177308-0d34-0410-b5e6-96231b3b80d8		2013-05-23 19:11:20 +00:00
..
Analysis
Archive
Assembler
Bindings/Ocaml
Bitcode
BugPoint
CodeGen	ARM: implement @llvm.readcyclecounter intrinsic	2013-05-23 19:11:20 +00:00
DebugInfo	Solidify the assumption that a DW_TAG_subprogram's type is a DW_TAG_subroutine_type	2013-05-22 23:22:18 +00:00
ExecutionEngine	Disable remote MCJIT on pre-v6 ARM	2013-05-20 07:46:06 +00:00
Feature
FileCheck
Instrumentation	[msan] A no-op implementation of VarArg handling.	2013-05-21 12:27:47 +00:00
Integer
JitListener
Linker
MC	VSTn instructions have a number of encoding constraints which are not implemented. I have added these using wrapper methods around the original custom decoder (incidentally - this is a huge poorly written method that should be cleaned up. I have left it as is since the changes would be much to hard to review).	2013-05-20 14:57:05 +00:00
Object	Use std::list so that we have a stable iterator.	2013-05-21 18:53:50 +00:00
Other
TableGen
tools
Transforms	SLPVectorizer: Change the order in which new instructions are added to the function.	2013-05-22 19:47:32 +00:00
Unit
Verifier
YAMLParser
CMakeLists.txt
lit.cfg
lit.site.cfg.in
Makefile	add polly to check-all	2013-05-20 18:49:15 +00:00
Makefile.tests
TestRunner.sh