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db703aaedd
MCOperand::Create*() methods renamed to MCOperand::create*(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237275 91177308-0d34-0410-b5e6-96231b3b80d8
641 lines
21 KiB
C++
641 lines
21 KiB
C++
//===-- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Thumb-2 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "Thumb2InstrInfo.h"
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#include "ARMConstantPoolValue.h"
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#include "ARMMachineFunctionInfo.h"
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#include "MCTargetDesc/ARMAddressingModes.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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static cl::opt<bool>
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OldT2IfCvt("old-thumb2-ifcvt", cl::Hidden,
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cl::desc("Use old-style Thumb2 if-conversion heuristics"),
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cl::init(false));
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Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
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: ARMBaseInstrInfo(STI), RI() {}
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/// getNoopForMachoTarget - Return the noop instruction to use for a noop.
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void Thumb2InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
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NopInst.setOpcode(ARM::tHINT);
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NopInst.addOperand(MCOperand::createImm(0));
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NopInst.addOperand(MCOperand::createImm(ARMCC::AL));
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NopInst.addOperand(MCOperand::createReg(0));
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}
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unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
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// FIXME
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return 0;
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}
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void
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Thumb2InstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
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MachineBasicBlock *NewDest) const {
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MachineBasicBlock *MBB = Tail->getParent();
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ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
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if (!AFI->hasITBlocks()) {
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TargetInstrInfo::ReplaceTailWithBranchTo(Tail, NewDest);
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return;
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}
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// If the first instruction of Tail is predicated, we may have to update
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// the IT instruction.
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unsigned PredReg = 0;
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ARMCC::CondCodes CC = getInstrPredicate(Tail, PredReg);
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MachineBasicBlock::iterator MBBI = Tail;
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if (CC != ARMCC::AL)
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// Expecting at least the t2IT instruction before it.
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--MBBI;
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// Actually replace the tail.
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TargetInstrInfo::ReplaceTailWithBranchTo(Tail, NewDest);
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// Fix up IT.
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if (CC != ARMCC::AL) {
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MachineBasicBlock::iterator E = MBB->begin();
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unsigned Count = 4; // At most 4 instructions in an IT block.
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while (Count && MBBI != E) {
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if (MBBI->isDebugValue()) {
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--MBBI;
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continue;
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}
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if (MBBI->getOpcode() == ARM::t2IT) {
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unsigned Mask = MBBI->getOperand(1).getImm();
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if (Count == 4)
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MBBI->eraseFromParent();
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else {
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unsigned MaskOn = 1 << Count;
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unsigned MaskOff = ~(MaskOn - 1);
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MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);
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}
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return;
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}
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--MBBI;
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--Count;
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}
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// Ctrl flow can reach here if branch folding is run before IT block
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// formation pass.
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}
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}
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bool
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Thumb2InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI) const {
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while (MBBI->isDebugValue()) {
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++MBBI;
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if (MBBI == MBB.end())
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return false;
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}
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unsigned PredReg = 0;
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return getITInstrPredicate(MBBI, PredReg) == ARMCC::AL;
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}
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void Thumb2InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const {
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// Handle SPR, DPR, and QPR copies.
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if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
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return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc)));
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}
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void Thumb2InstrInfo::
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storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned SrcReg, bool isKill, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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MachineFunction &MF = *MBB.getParent();
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MachineFrameInfo &MFI = *MF.getFrameInfo();
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MachineMemOperand *MMO =
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MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
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MachineMemOperand::MOStore,
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MFI.getObjectSize(FI),
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MFI.getObjectAlignment(FI));
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if (RC == &ARM::GPRRegClass || RC == &ARM::tGPRRegClass ||
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RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass ||
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RC == &ARM::GPRnopcRegClass) {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12))
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.addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FI).addImm(0).addMemOperand(MMO));
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return;
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}
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if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
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// Thumb2 STRD expects its dest-registers to be in rGPR. Not a problem for
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// gsub_0, but needs an extra constraint for gsub_1 (which could be sp
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// otherwise).
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MachineRegisterInfo *MRI = &MF.getRegInfo();
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MRI->constrainRegClass(SrcReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
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MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8));
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AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
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AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
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MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
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AddDefaultPred(MIB);
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return;
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}
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ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI);
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}
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void Thumb2InstrInfo::
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loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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MachineFunction &MF = *MBB.getParent();
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MachineFrameInfo &MFI = *MF.getFrameInfo();
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MachineMemOperand *MMO =
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MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
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MachineMemOperand::MOLoad,
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MFI.getObjectSize(FI),
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MFI.getObjectAlignment(FI));
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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if (RC == &ARM::GPRRegClass || RC == &ARM::tGPRRegClass ||
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RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass ||
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RC == &ARM::GPRnopcRegClass) {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
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.addFrameIndex(FI).addImm(0).addMemOperand(MMO));
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return;
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}
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if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
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// Thumb2 LDRD expects its dest-registers to be in rGPR. Not a problem for
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// gsub_0, but needs an extra constraint for gsub_1 (which could be sp
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// otherwise).
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MachineRegisterInfo *MRI = &MF.getRegInfo();
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MRI->constrainRegClass(DestReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
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MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8));
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AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
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AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
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MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
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AddDefaultPred(MIB);
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if (TargetRegisterInfo::isPhysicalRegister(DestReg))
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MIB.addReg(DestReg, RegState::ImplicitDefine);
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return;
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}
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ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI);
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}
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void
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Thumb2InstrInfo::expandLoadStackGuard(MachineBasicBlock::iterator MI,
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Reloc::Model RM) const {
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if (RM == Reloc::PIC_)
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expandLoadStackGuardBase(MI, ARM::t2MOV_ga_pcrel, ARM::t2LDRi12, RM);
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else
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expandLoadStackGuardBase(MI, ARM::t2MOVi32imm, ARM::t2LDRi12, RM);
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}
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void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI, DebugLoc dl,
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unsigned DestReg, unsigned BaseReg, int NumBytes,
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ARMCC::CondCodes Pred, unsigned PredReg,
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const ARMBaseInstrInfo &TII, unsigned MIFlags) {
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if (NumBytes == 0 && DestReg != BaseReg) {
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BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
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.addReg(BaseReg, RegState::Kill)
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.addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
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return;
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}
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bool isSub = NumBytes < 0;
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if (isSub) NumBytes = -NumBytes;
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// If profitable, use a movw or movt to materialize the offset.
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// FIXME: Use the scavenger to grab a scratch register.
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if (DestReg != ARM::SP && DestReg != BaseReg &&
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NumBytes >= 4096 &&
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ARM_AM::getT2SOImmVal(NumBytes) == -1) {
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bool Fits = false;
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if (NumBytes < 65536) {
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// Use a movw to materialize the 16-bit constant.
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BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
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.addImm(NumBytes)
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.addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
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Fits = true;
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} else if ((NumBytes & 0xffff) == 0) {
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// Use a movt to materialize the 32-bit constant.
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BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
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.addReg(DestReg)
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.addImm(NumBytes >> 16)
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.addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
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Fits = true;
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}
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if (Fits) {
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if (isSub) {
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BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
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.addReg(BaseReg)
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.addReg(DestReg, RegState::Kill)
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.addImm((unsigned)Pred).addReg(PredReg).addReg(0)
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.setMIFlags(MIFlags);
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} else {
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// Here we know that DestReg is not SP but we do not
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// know anything about BaseReg. t2ADDrr is an invalid
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// instruction is SP is used as the second argument, but
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// is fine if SP is the first argument. To be sure we
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// do not generate invalid encoding, put BaseReg first.
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BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
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.addReg(BaseReg)
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.addReg(DestReg, RegState::Kill)
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.addImm((unsigned)Pred).addReg(PredReg).addReg(0)
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.setMIFlags(MIFlags);
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}
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return;
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}
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}
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while (NumBytes) {
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unsigned ThisVal = NumBytes;
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unsigned Opc = 0;
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if (DestReg == ARM::SP && BaseReg != ARM::SP) {
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// mov sp, rn. Note t2MOVr cannot be used.
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AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),DestReg)
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.addReg(BaseReg).setMIFlags(MIFlags));
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BaseReg = ARM::SP;
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continue;
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}
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bool HasCCOut = true;
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if (BaseReg == ARM::SP) {
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// sub sp, sp, #imm7
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if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) {
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assert((ThisVal & 3) == 0 && "Stack update is not multiple of 4?");
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Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
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AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
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.addReg(BaseReg).addImm(ThisVal/4).setMIFlags(MIFlags));
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NumBytes = 0;
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continue;
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}
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// sub rd, sp, so_imm
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Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
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if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
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NumBytes = 0;
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} else {
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// FIXME: Move this to ARMAddressingModes.h?
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unsigned RotAmt = countLeadingZeros(ThisVal);
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ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
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NumBytes &= ~ThisVal;
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assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
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"Bit extraction didn't work?");
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}
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} else {
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assert(DestReg != ARM::SP && BaseReg != ARM::SP);
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Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
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if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
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NumBytes = 0;
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} else if (ThisVal < 4096) {
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Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
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HasCCOut = false;
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NumBytes = 0;
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} else {
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// FIXME: Move this to ARMAddressingModes.h?
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unsigned RotAmt = countLeadingZeros(ThisVal);
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ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
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NumBytes &= ~ThisVal;
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assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
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"Bit extraction didn't work?");
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}
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}
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// Build the new ADD / SUB.
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MachineInstrBuilder MIB =
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AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
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.addReg(BaseReg, RegState::Kill)
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.addImm(ThisVal)).setMIFlags(MIFlags);
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if (HasCCOut)
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AddDefaultCC(MIB);
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BaseReg = DestReg;
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}
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}
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static unsigned
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negativeOffsetOpcode(unsigned opcode)
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{
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switch (opcode) {
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case ARM::t2LDRi12: return ARM::t2LDRi8;
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case ARM::t2LDRHi12: return ARM::t2LDRHi8;
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case ARM::t2LDRBi12: return ARM::t2LDRBi8;
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case ARM::t2LDRSHi12: return ARM::t2LDRSHi8;
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case ARM::t2LDRSBi12: return ARM::t2LDRSBi8;
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case ARM::t2STRi12: return ARM::t2STRi8;
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case ARM::t2STRBi12: return ARM::t2STRBi8;
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case ARM::t2STRHi12: return ARM::t2STRHi8;
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case ARM::t2PLDi12: return ARM::t2PLDi8;
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case ARM::t2LDRi8:
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case ARM::t2LDRHi8:
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case ARM::t2LDRBi8:
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case ARM::t2LDRSHi8:
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case ARM::t2LDRSBi8:
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case ARM::t2STRi8:
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case ARM::t2STRBi8:
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case ARM::t2STRHi8:
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case ARM::t2PLDi8:
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return opcode;
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default:
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break;
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}
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return 0;
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}
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static unsigned
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positiveOffsetOpcode(unsigned opcode)
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{
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switch (opcode) {
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case ARM::t2LDRi8: return ARM::t2LDRi12;
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case ARM::t2LDRHi8: return ARM::t2LDRHi12;
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case ARM::t2LDRBi8: return ARM::t2LDRBi12;
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case ARM::t2LDRSHi8: return ARM::t2LDRSHi12;
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case ARM::t2LDRSBi8: return ARM::t2LDRSBi12;
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case ARM::t2STRi8: return ARM::t2STRi12;
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case ARM::t2STRBi8: return ARM::t2STRBi12;
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case ARM::t2STRHi8: return ARM::t2STRHi12;
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case ARM::t2PLDi8: return ARM::t2PLDi12;
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case ARM::t2LDRi12:
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case ARM::t2LDRHi12:
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case ARM::t2LDRBi12:
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case ARM::t2LDRSHi12:
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case ARM::t2LDRSBi12:
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case ARM::t2STRi12:
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case ARM::t2STRBi12:
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case ARM::t2STRHi12:
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case ARM::t2PLDi12:
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return opcode;
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default:
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break;
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}
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return 0;
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}
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static unsigned
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immediateOffsetOpcode(unsigned opcode)
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{
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switch (opcode) {
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case ARM::t2LDRs: return ARM::t2LDRi12;
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case ARM::t2LDRHs: return ARM::t2LDRHi12;
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case ARM::t2LDRBs: return ARM::t2LDRBi12;
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case ARM::t2LDRSHs: return ARM::t2LDRSHi12;
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case ARM::t2LDRSBs: return ARM::t2LDRSBi12;
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case ARM::t2STRs: return ARM::t2STRi12;
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case ARM::t2STRBs: return ARM::t2STRBi12;
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case ARM::t2STRHs: return ARM::t2STRHi12;
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case ARM::t2PLDs: return ARM::t2PLDi12;
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case ARM::t2LDRi12:
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case ARM::t2LDRHi12:
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case ARM::t2LDRBi12:
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case ARM::t2LDRSHi12:
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case ARM::t2LDRSBi12:
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case ARM::t2STRi12:
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case ARM::t2STRBi12:
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case ARM::t2STRHi12:
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case ARM::t2PLDi12:
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case ARM::t2LDRi8:
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case ARM::t2LDRHi8:
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case ARM::t2LDRBi8:
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case ARM::t2LDRSHi8:
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case ARM::t2LDRSBi8:
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case ARM::t2STRi8:
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case ARM::t2STRBi8:
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case ARM::t2STRHi8:
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case ARM::t2PLDi8:
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return opcode;
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default:
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break;
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}
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return 0;
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}
|
|
|
|
bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
|
|
unsigned FrameReg, int &Offset,
|
|
const ARMBaseInstrInfo &TII) {
|
|
unsigned Opcode = MI.getOpcode();
|
|
const MCInstrDesc &Desc = MI.getDesc();
|
|
unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
|
|
bool isSub = false;
|
|
|
|
// Memory operands in inline assembly always use AddrModeT2_i12.
|
|
if (Opcode == ARM::INLINEASM)
|
|
AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2?
|
|
|
|
if (Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {
|
|
Offset += MI.getOperand(FrameRegIdx+1).getImm();
|
|
|
|
unsigned PredReg;
|
|
if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
|
|
// Turn it into a move.
|
|
MI.setDesc(TII.get(ARM::tMOVr));
|
|
MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
|
|
// Remove offset and remaining explicit predicate operands.
|
|
do MI.RemoveOperand(FrameRegIdx+1);
|
|
while (MI.getNumOperands() > FrameRegIdx+1);
|
|
MachineInstrBuilder MIB(*MI.getParent()->getParent(), &MI);
|
|
AddDefaultPred(MIB);
|
|
return true;
|
|
}
|
|
|
|
bool HasCCOut = Opcode != ARM::t2ADDri12;
|
|
|
|
if (Offset < 0) {
|
|
Offset = -Offset;
|
|
isSub = true;
|
|
MI.setDesc(TII.get(ARM::t2SUBri));
|
|
} else {
|
|
MI.setDesc(TII.get(ARM::t2ADDri));
|
|
}
|
|
|
|
// Common case: small offset, fits into instruction.
|
|
if (ARM_AM::getT2SOImmVal(Offset) != -1) {
|
|
MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
|
|
MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
|
|
// Add cc_out operand if the original instruction did not have one.
|
|
if (!HasCCOut)
|
|
MI.addOperand(MachineOperand::CreateReg(0, false));
|
|
Offset = 0;
|
|
return true;
|
|
}
|
|
// Another common case: imm12.
|
|
if (Offset < 4096 &&
|
|
(!HasCCOut || MI.getOperand(MI.getNumOperands()-1).getReg() == 0)) {
|
|
unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
|
|
MI.setDesc(TII.get(NewOpc));
|
|
MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
|
|
MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
|
|
// Remove the cc_out operand.
|
|
if (HasCCOut)
|
|
MI.RemoveOperand(MI.getNumOperands()-1);
|
|
Offset = 0;
|
|
return true;
|
|
}
|
|
|
|
// Otherwise, extract 8 adjacent bits from the immediate into this
|
|
// t2ADDri/t2SUBri.
|
|
unsigned RotAmt = countLeadingZeros<unsigned>(Offset);
|
|
unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt);
|
|
|
|
// We will handle these bits from offset, clear them.
|
|
Offset &= ~ThisImmVal;
|
|
|
|
assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 &&
|
|
"Bit extraction didn't work?");
|
|
MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
|
|
// Add cc_out operand if the original instruction did not have one.
|
|
if (!HasCCOut)
|
|
MI.addOperand(MachineOperand::CreateReg(0, false));
|
|
|
|
} else {
|
|
|
|
// AddrMode4 and AddrMode6 cannot handle any offset.
|
|
if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
|
|
return false;
|
|
|
|
// AddrModeT2_so cannot handle any offset. If there is no offset
|
|
// register then we change to an immediate version.
|
|
unsigned NewOpc = Opcode;
|
|
if (AddrMode == ARMII::AddrModeT2_so) {
|
|
unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg();
|
|
if (OffsetReg != 0) {
|
|
MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
|
|
return Offset == 0;
|
|
}
|
|
|
|
MI.RemoveOperand(FrameRegIdx+1);
|
|
MI.getOperand(FrameRegIdx+1).ChangeToImmediate(0);
|
|
NewOpc = immediateOffsetOpcode(Opcode);
|
|
AddrMode = ARMII::AddrModeT2_i12;
|
|
}
|
|
|
|
unsigned NumBits = 0;
|
|
unsigned Scale = 1;
|
|
if (AddrMode == ARMII::AddrModeT2_i8 || AddrMode == ARMII::AddrModeT2_i12) {
|
|
// i8 supports only negative, and i12 supports only positive, so
|
|
// based on Offset sign convert Opcode to the appropriate
|
|
// instruction
|
|
Offset += MI.getOperand(FrameRegIdx+1).getImm();
|
|
if (Offset < 0) {
|
|
NewOpc = negativeOffsetOpcode(Opcode);
|
|
NumBits = 8;
|
|
isSub = true;
|
|
Offset = -Offset;
|
|
} else {
|
|
NewOpc = positiveOffsetOpcode(Opcode);
|
|
NumBits = 12;
|
|
}
|
|
} else if (AddrMode == ARMII::AddrMode5) {
|
|
// VFP address mode.
|
|
const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
|
|
int InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
|
|
if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
|
|
InstrOffs *= -1;
|
|
NumBits = 8;
|
|
Scale = 4;
|
|
Offset += InstrOffs * 4;
|
|
assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
|
|
if (Offset < 0) {
|
|
Offset = -Offset;
|
|
isSub = true;
|
|
}
|
|
} else if (AddrMode == ARMII::AddrModeT2_i8s4) {
|
|
Offset += MI.getOperand(FrameRegIdx + 1).getImm() * 4;
|
|
NumBits = 10; // 8 bits scaled by 4
|
|
// MCInst operand expects already scaled value.
|
|
Scale = 1;
|
|
assert((Offset & 3) == 0 && "Can't encode this offset!");
|
|
} else {
|
|
llvm_unreachable("Unsupported addressing mode!");
|
|
}
|
|
|
|
if (NewOpc != Opcode)
|
|
MI.setDesc(TII.get(NewOpc));
|
|
|
|
MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1);
|
|
|
|
// Attempt to fold address computation
|
|
// Common case: small offset, fits into instruction.
|
|
int ImmedOffset = Offset / Scale;
|
|
unsigned Mask = (1 << NumBits) - 1;
|
|
if ((unsigned)Offset <= Mask * Scale) {
|
|
// Replace the FrameIndex with fp/sp
|
|
MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
|
|
if (isSub) {
|
|
if (AddrMode == ARMII::AddrMode5)
|
|
// FIXME: Not consistent.
|
|
ImmedOffset |= 1 << NumBits;
|
|
else
|
|
ImmedOffset = -ImmedOffset;
|
|
}
|
|
ImmOp.ChangeToImmediate(ImmedOffset);
|
|
Offset = 0;
|
|
return true;
|
|
}
|
|
|
|
// Otherwise, offset doesn't fit. Pull in what we can to simplify
|
|
ImmedOffset = ImmedOffset & Mask;
|
|
if (isSub) {
|
|
if (AddrMode == ARMII::AddrMode5)
|
|
// FIXME: Not consistent.
|
|
ImmedOffset |= 1 << NumBits;
|
|
else {
|
|
ImmedOffset = -ImmedOffset;
|
|
if (ImmedOffset == 0)
|
|
// Change the opcode back if the encoded offset is zero.
|
|
MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
|
|
}
|
|
}
|
|
ImmOp.ChangeToImmediate(ImmedOffset);
|
|
Offset &= ~(Mask*Scale);
|
|
}
|
|
|
|
Offset = (isSub) ? -Offset : Offset;
|
|
return Offset == 0;
|
|
}
|
|
|
|
ARMCC::CondCodes
|
|
llvm::getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
|
|
unsigned Opc = MI->getOpcode();
|
|
if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
|
|
return ARMCC::AL;
|
|
return getInstrPredicate(MI, PredReg);
|
|
}
|