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priority function. Instead, just iterate over the AllNodes list, which is already in topological order. This eliminates a fair amount of bookkeeping, and speeds up the isel phase by about 15% on many testcases. The impact on most targets is that AddToISelQueue calls can be simply removed. In the x86 target, there are two additional notable changes. The rule-bending AND+SHIFT optimization in MatchAddress that creates new pre-isel nodes during isel is now a little more verbose, but more robust. Instead of either creating an invalid DAG or creating an invalid topological sort, as it has historically done, it can now just insert the new nodes into the node list at a position where they will be consistent with the topological ordering. Also, the address-matching code has logic that checked to see if a node was "already selected". However, when a node is selected, it has all its uses taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any further visits from MatchAddress. This code is now removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58748 91177308-0d34-0410-b5e6-96231b3b80d8 |
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|---|---|---|
| .. | ||
| CellSDKIntrinsics.td | ||
| CMakeLists.txt | ||
| Makefile | ||
| README.txt | ||
| SPU.h | ||
| SPU.td | ||
| SPUAsmPrinter.cpp | ||
| SPUCallingConv.td | ||
| SPUFrameInfo.cpp | ||
| SPUFrameInfo.h | ||
| SPUHazardRecognizers.cpp | ||
| SPUHazardRecognizers.h | ||
| SPUInstrBuilder.h | ||
| SPUInstrFormats.td | ||
| SPUInstrInfo.cpp | ||
| SPUInstrInfo.h | ||
| SPUInstrInfo.td | ||
| SPUISelDAGToDAG.cpp | ||
| SPUISelLowering.cpp | ||
| SPUISelLowering.h | ||
| SPUMachineFunction.h | ||
| SPUNodes.td | ||
| SPUOperands.td | ||
| SPURegisterInfo.cpp | ||
| SPURegisterInfo.h | ||
| SPURegisterInfo.td | ||
| SPURegisterNames.h | ||
| SPUSchedule.td | ||
| SPUSubtarget.cpp | ||
| SPUSubtarget.h | ||
| SPUTargetAsmInfo.cpp | ||
| SPUTargetAsmInfo.h | ||
| SPUTargetMachine.cpp | ||
| SPUTargetMachine.h | ||
//===- README.txt - Notes for improving CellSPU-specific code gen ---------===//
This code was contributed by a team from the Computer Systems Research
Department in The Aerospace Corporation:
- Scott Michel (head bottle washer and much of the non-floating point
instructions)
- Mark Thomas (floating point instructions)
- Michael AuYeung (intrinsics)
- Chandler Carruth (LLVM expertise)
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT, OR
OTHERWISE. IN NO EVENT SHALL THE AEROSPACE CORPORATION BE LIABLE FOR DAMAGES
OF ANY KIND OR NATURE WHETHER BASED IN CONTRACT, TORT, OR OTHERWISE ARISING
OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE INCLUDING, WITHOUT
LIMITATION, DAMAGES RESULTING FROM LOST OR CONTAMINATED DATA, LOST PROFITS OR
REVENUE, COMPUTER MALFUNCTION, OR FOR ANY SPECIAL, INCIDENTAL, CONSEQUENTIAL,
OR PUNITIVE DAMAGES, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES OR
SUCH DAMAGES ARE FORESEEABLE.
---------------------------------------------------------------------------
--WARNING--:
--WARNING--: The CellSPU work is work-in-progress and "alpha" quality code.
--WARNING--:
If you are brave enough to try this code or help to hack on it, be sure
to add 'spu' to configure's --enable-targets option, e.g.:
./configure <your_configure_flags_here> \
--enable-targets=x86,x86_64,powerpc,spu
---------------------------------------------------------------------------
TODO:
* Finish branch instructions, branch prediction
These instructions were started, but only insofar as to get llvm-gcc-4.2's
crtbegin.ll working (which doesn't.)
* Double floating point support
This was started. "What's missing?" to be filled in.
* Intrinsics
Lots of progress. "What's missing/incomplete?" to be filled in.
===-------------------------------------------------------------------------===