Jingyue Wu dde12814c7 [NVPTX] declare no vector registers ... Summary: Without this patch, LoopVectorizer in certain cases (see loop-vectorize.ll) produces code with complex control flow which hurts later optimizations. Since NVPTX doesn't have vector registers in LLVM's sense (NVPTXTTI::getRegisterBitWidth(true) == 32), we for now declare no vector registers to effectively disable loop vectorization. Reviewers: jholewinski Subscribers: jingyue, llvm-commits, jholewinski Differential Revision: http://reviews.llvm.org/D11089 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241884 91177308-0d34-0410-b5e6-96231b3b80d8		2015-07-10 04:31:56 +00:00
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AArch64	[AArch64] Select SBFIZ or UBFIZ instead of left + right shifts	2015-07-09 14:33:38 +00:00
AMDGPU	AMDGPU/SI: Add debugging subtarget feature for DS offsets	2015-07-06 16:01:58 +00:00
ARM	Fix test case to unbreak build.	2015-07-07 14:45:12 +00:00
BPF
CPP
Generic	llc: Add a 'run-pass' option.	2015-07-06 17:44:26 +00:00
Hexagon	[Hexagon] Add support for atomic RMW operations	2015-07-09 14:51:21 +00:00
Inputs
Mips
MIR	MIR Serialization: Serialize the virtual register definitions.	2015-07-09 22:23:13 +00:00
MSP430
NVPTX	[NVPTX] declare no vector registers	2015-07-10 04:31:56 +00:00
PowerPC	Add missing builtins to the PPC back end for ABI compliance (vol. 2)	2015-07-05 06:03:51 +00:00
SPARC	[SPARC] Cleanup handling of the Y/ASR registers.	2015-07-08 16:25:12 +00:00
SystemZ
Thumb
Thumb2
WebAssembly	[WebAssembly] Create a CodeGen unittest directory.	2015-07-06 23:14:57 +00:00
WinEH	[WinEH] Make sure LSDA tables are 4 byte aligned	2015-07-10 00:08:49 +00:00
X86	[WinEH] Make sure LSDA tables are 4 byte aligned	2015-07-10 00:08:49 +00:00
XCore