1
0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-30 02:32:08 +00:00
llvm-6502/test/TableGen/usevalname.td
Bruno Cardoso Lopes 81cd7ffe45 Fix a tblgen bug.
Given the pattern below as an example:
list<dag> Pattern = [(set RC:$dst, (v4f32 (shufp:src3 RC:$src1,
                            (mem_frag addr:$src2))))];

The right reference resolving should lead to:
list<dag> Pattern = [(set VR128:$dst, (v4f32 (shufp:src3 VR128:$src1,
                            (mem_frag addr:$src2))))];
But was yielding:
list<dag> Pattern = [(set VR128:$dst, (v4f32 (shufp VR128:$src1,
                            (mem_frag addr:$src2))))];

Fix this by passing the right name when creating a new DagInit node.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106670 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 19:50:39 +00:00

25 lines
396 B
TableGen

// RUN: tblgen %s | FileCheck %s
// XFAIL: vg_leak
class Instr<list<dag> pat> {
list<dag> Pattern = pat;
}
class Reg {
int a = 3;
}
def VR128 : Reg;
def mem_frag;
def set;
def addr;
def shufp : Reg;
multiclass shuffle<Reg RC> {
def rri : Instr<[(set RC:$dst, (shufp:$src3
RC:$src1, RC:$src2))]>;
}
// CHECK: shufp:src3
defm ADD : shuffle<VR128>;