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https://github.com/c64scene-ar/llvm-6502.git
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2061dcf0e4
In X86FastISel::X86SelectStore(), improperly aligned stores are rejected and handled by the DAG-based ISel. However, X86FastISel::X86SelectLoad() makes no such requirement. There doesn't appear to be an x86 architectural correctness issue with allowing potentially unaligned store instructions. This patch removes this restriction. Patch by Jim Stichnot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179774 91177308-0d34-0410-b5e6-96231b3b80d8
19 lines
456 B
LLVM
19 lines
456 B
LLVM
; RUN: llc -mtriple=x86_64-none-linux -fast-isel -fast-isel-abort < %s | FileCheck %s
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; RUN: llc -mtriple=i686-none-linux -fast-isel -fast-isel-abort < %s | FileCheck %s
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define i32 @test_store_32(i32* nocapture %addr, i32 %value) {
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entry:
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store i32 %value, i32* %addr, align 1
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ret i32 %value
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}
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; CHECK: ret
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define i16 @test_store_16(i16* nocapture %addr, i16 %value) {
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entry:
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store i16 %value, i16* %addr, align 1
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ret i16 %value
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}
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; CHECK: ret
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