llvm-6502/lib/CodeGen
Chris Lattner fad86b003a Rework the routines that convert AP[S]Int into a string. Now, instead of
returning an std::string by value, it fills in a SmallString/SmallVector
passed in.  This significantly reduces string thrashing in some cases.

More specifically, this:
 - Adds an operator<< and a print method for APInt that allows you to 
   directly send them to an ostream.
 - Reimplements APInt::toString to be much simpler and more efficient
   algorithmically in addition to not thrashing strings quite as much.

This speeds up llvm-dis on kc++ by 7%, and may also slightly speed up the
asmprinter.  This also fixes a bug I introduced into the asmwriter in a
previous patch w.r.t. alias printing.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54873 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-17 07:19:36 +00:00
..
SelectionDAG Rework the routines that convert AP[S]Int into a string. Now, instead of 2008-08-17 07:19:36 +00:00
AsmPrinter.cpp Rework the routines that convert AP[S]Int into a string. Now, instead of 2008-08-17 07:19:36 +00:00
BranchFolding.cpp Convert uses of std::vector in TargetInstrInfo to SmallVector. This change had to be propoagated down into all the targets and up into all clients of this API. 2008-08-14 22:49:33 +00:00
Collector.cpp Use of operator* is redundant and confusing here. 2008-07-07 20:08:05 +00:00
CollectorMetadata.cpp Add a new (simple) StringMap::clear method, patch by Pratik 2008-07-02 05:26:32 +00:00
Collectors.cpp Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
DwarfWriter.cpp Move SLEB/ULEB size calculation routines from AsmPrinter to TargetAsmInfo. This makes JIT asmprinter-free. 2008-08-16 12:57:46 +00:00
ELFWriter.cpp Add CommonLinkage; currently tentative definitions 2008-05-14 20:12:51 +00:00
ELFWriter.h Don't include <map> in Pass.h, which doesn't need it. This requires 2008-03-21 23:51:57 +00:00
IfConversion.cpp Convert uses of std::vector in TargetInstrInfo to SmallVector. This change had to be propoagated down into all the targets and up into all clients of this API. 2008-08-14 22:49:33 +00:00
IntrinsicLowering.cpp API change for {BinaryOperator|CmpInst|CastInst}::create*() --> Create. Legacy interfaces will be in place for some time. (Merge from use-diet branch.) 2008-05-16 19:29:10 +00:00
LiveInterval.cpp Use empty() instead of begin() == end(). 2008-08-14 18:13:49 +00:00
LiveIntervalAnalysis.cpp Expunge the last uses of std::map from LiveIntervals. 2008-08-13 22:28:50 +00:00
LiveStackAnalysis.cpp Add a stack slot coloring pass. Not yet enabled. 2008-06-04 09:18:41 +00:00
LiveVariables.cpp Use SmallSet instead of std::set to save allocations. 2008-08-14 23:41:38 +00:00
LLVMTargetMachine.cpp Don't run stack slot coloring if -fast. 2008-06-30 22:33:16 +00:00
LoopAligner.cpp Use empty() instead of begin() == end(). 2008-08-14 18:13:49 +00:00
LowerSubregs.cpp Re-enable elimination of unnecessary SUBREG_TO_REG instructions in 2008-08-07 02:54:50 +00:00
MachineBasicBlock.cpp Fold the useful features of alist and alist_node into ilist, and 2008-07-28 21:51:04 +00:00
MachineDominators.cpp Change class' public PassInfo variables to by initialized with the 2008-05-13 02:05:11 +00:00
MachineFunction.cpp Fold the useful features of alist and alist_node into ilist, and 2008-07-28 21:51:04 +00:00
MachineInstr.cpp Move MachineInstr::getOpcode inline. 2008-08-14 23:25:30 +00:00
MachineLICM.cpp Prevent option name conflict. 2008-07-07 05:42:27 +00:00
MachineLoopInfo.cpp Change class' public PassInfo variables to by initialized with the 2008-05-13 02:05:11 +00:00
MachineModuleInfo.cpp Make the DICountVisitor not a visitor. This keeps us from calling virtual 2008-07-09 06:02:33 +00:00
MachinePassRegistry.cpp Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
MachineRegisterInfo.cpp Assert that all MachineInstrs update PhysRegUseDefLists in 2008-07-07 19:55:35 +00:00
MachineSink.cpp Clean up the use of static and anonymous namespaces. This turned up 2008-05-13 00:00:25 +00:00
MachOWriter.cpp Use isSingleValueType instead of isFirstClassType to 2008-05-23 00:17:26 +00:00
MachOWriter.h Don't include <map> in Pass.h, which doesn't need it. This requires 2008-03-21 23:51:57 +00:00
Makefile remove attribution from lib Makefiles. 2007-12-29 20:09:26 +00:00
OcamlCollector.cpp Fix some typos. Apparently I think C needs a power-of operator. 2008-08-09 03:48:46 +00:00
Passes.cpp Clean up the use of static and anonymous namespaces. This turned up 2008-05-13 00:00:25 +00:00
PHIElimination.cpp Pool-allocation for MachineInstrs, MachineBasicBlocks, and 2008-07-07 23:14:23 +00:00
PhysRegTracker.h Rename MRegisterInfo to TargetRegisterInfo. 2008-02-10 18:45:23 +00:00
PostRASchedulerList.cpp don't create the post-ra scheduler unless it is enabled. 2008-01-14 19:00:06 +00:00
PrologEpilogInserter.cpp Fix a comment to say nonnegative instead of positive. 2008-07-16 15:57:10 +00:00
PseudoSourceValue.cpp Enable rematerialization of constants using AliasAnalysis::pointsToConstantMemory, 2008-07-25 00:02:30 +00:00
README.txt Enable stack coloring by default. 2008-06-06 19:52:44 +00:00
RegAllocBigBlock.cpp Clean up the use of static and anonymous namespaces. This turned up 2008-05-13 00:00:25 +00:00
RegAllocLinearScan.cpp Convert several std::vectors over to SmallVector, and use reserve() as appropriate for cases where std::vector is still used. 2008-08-15 18:49:41 +00:00
RegAllocLocal.cpp Change StackSlotForVirtReg (which maps vregs to frame indices) from std::map to IndexedMap. 2008-07-10 18:23:23 +00:00
RegAllocSimple.cpp Reuse the MO variable instead of recomputing it in RegAllocLocal. 2008-07-09 20:12:26 +00:00
RegisterCoalescer.cpp Clean up the use of static and anonymous namespaces. This turned up 2008-05-13 00:00:25 +00:00
RegisterScavenging.cpp Minor const-correctness fixes. 2008-07-07 20:06:06 +00:00
ShadowStackCollector.cpp Have IRBuilder take a template argument on whether or not to preserve 2008-08-08 19:39:37 +00:00
SimpleRegisterCoalescing.cpp Convert uses of std::vector in TargetInstrInfo to SmallVector. This change had to be propoagated down into all the targets and up into all clients of this API. 2008-08-14 22:49:33 +00:00
SimpleRegisterCoalescing.h Fix a compile-time regression introduced by my heuristic-changing patch. I forgot 2008-07-23 19:47:27 +00:00
StackSlotColoring.cpp Make stack slot coloring's debug output more consistent with 2008-07-10 19:49:32 +00:00
StrongPHIElimination.cpp Use empty() instead of begin() == end(). 2008-08-14 18:13:49 +00:00
TargetInstrInfoImpl.cpp Convert uses of std::vector in TargetInstrInfo to SmallVector. This change had to be propoagated down into all the targets and up into all clients of this API. 2008-08-14 22:49:33 +00:00
TwoAddressInstructionPass.cpp - Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. 2008-07-03 09:09:37 +00:00
UnreachableBlockElim.cpp Remove more uses of std::set. 2008-08-14 21:01:00 +00:00
VirtRegMap.cpp Fix PR2596: out of bound reference. 2008-08-05 21:51:46 +00:00
VirtRegMap.h Move #include to right place. 2008-06-04 09:16:33 +00:00

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelyhood the store may become dead.

//===---------------------------------------------------------------------===//

I think we should have a "hasSideEffects" flag (which is automatically set for
stuff that "isLoad" "isCall" etc), and the remat pass should eventually be able
to remat any instruction that has no side effects, if it can handle it and if
profitable.

For now, I'd suggest having the remat stuff work like this:

1. I need to spill/reload this thing.
2. Check to see if it has side effects.
3. Check to see if it is simple enough: e.g. it only has one register
destination and no register input.
4. If so, clone the instruction, do the xform, etc.

Advantages of this are:

1. the .td file describes the behavior of the instructions, not the way the
   algorithm should work.
2. as remat gets smarter in the future, we shouldn't have to be changing the .td
   files.
3. it is easier to explain what the flag means in the .td file, because you
   don't have to pull in the explanation of how the current remat algo works.

Some potential added complexities:

1. Some instructions have to be glued to it's predecessor or successor. All of
   the PC relative instructions and condition code setting instruction. We could
   mark them as hasSideEffects, but that's not quite right. PC relative loads
   from constantpools can be remat'ed, for example. But it requires more than
   just cloning the instruction. Some instructions can be remat'ed but it
   expands to more than one instruction. But allocator will have to make a
   decision.

4. As stated in 3, not as simple as cloning in some cases. The target will have
   to decide how to remat it. For example, an ARM 2-piece constant generation
   instruction is remat'ed as a load from constantpool.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
	ldr r3, [sp, #+4]
	add r3, r3, #3
	ldr r2, [sp, #+8]
	add r2, r2, #2
	ldr r1, [sp, #+4]  <==
	add r1, r1, #1
	ldr r0, [sp, #+4]
	add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvments:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4