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c4cc40c001
- Add TSFlags for the instruction formats. The idea here is to use as much encoding as possible from getBinaryCodeForInstr, and having TSFLags formats for that would make it easier to encode most part of the instructions (since Mips encodings are pretty straightforward) - Improve the mips mechanism for compilation callback - Add Mips specific code for invalidating the instruction cache - Next patch will address wrong tablegen encoding Commit msg added by my own but the patch is from Sasa Stankovic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139688 91177308-0d34-0410-b5e6-96231b3b80d8
110 lines
3.9 KiB
C++
110 lines
3.9 KiB
C++
//===- Memory.cpp - Memory Handling Support ---------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines some helpful functions for allocating memory and dealing
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// with memory mapped files
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Support/Memory.h"
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#include "llvm/Support/Valgrind.h"
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#include "llvm/Config/config.h"
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namespace llvm {
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using namespace sys;
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}
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// Include the platform-specific parts of this class.
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#ifdef LLVM_ON_UNIX
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#include "Unix/Memory.inc"
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#endif
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#ifdef LLVM_ON_WIN32
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#include "Windows/Memory.inc"
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#endif
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extern "C" void sys_icache_invalidate(const void *Addr, size_t len);
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/// ClearMipsCache - Invalidates instruction cache for Mips. This assembly code
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/// is copied from the MIPS32 Instruction Set Reference. Since the code ends
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/// with the return instruction "jr.hb ra" (Jump Register with Hazard Barrier),
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/// it must be implemented as a function (which is called from the
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/// InvalidateInstructionCache function). It cannot be directly inlined into
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/// InvalidateInstructionCache function, because in that case the epilog of
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/// InvalidateInstructionCache will not be executed.
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#if defined(__mips__)
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extern "C" void ClearMipsCache(const void* Addr, size_t Size);
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asm volatile(
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".text\n"
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".align 2\n"
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".globl ClearMipsCache\n"
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"ClearMipsCache:\n"
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".set noreorder\n"
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"beq $a1, $zero, 20f\n" /* If size==0, branch around */
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"nop\n"
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"addu $a1, $a0, $a1\n" /* Calculate end address + 1 */
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"rdhwr $v0, $1\n" /* Get step size for SYNCI */
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/* $1 is $HW_SYNCI_Step */
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"beq $v0, $zero, 20f\n" /* If no caches require synchronization, */
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/* branch around */
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"nop\n"
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"10: synci 0($a0)\n" /* Synchronize all caches around address */
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"sltu $v1, $a0, $a1\n" /* Compare current with end address */
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"bne $v1, $zero, 10b\n" /* Branch if more to do */
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"addu $a0, $a0, $v0\n" /* Add step size in delay slot */
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"sync\n" /* Clear memory hazards */
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"20: jr.hb $ra\n" /* Return, clearing instruction hazards */
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"nop\n"
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);
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#endif
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/// InvalidateInstructionCache - Before the JIT can run a block of code
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/// that has been emitted it must invalidate the instruction cache on some
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/// platforms.
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void llvm::sys::Memory::InvalidateInstructionCache(const void *Addr,
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size_t Len) {
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// icache invalidation for PPC and ARM.
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#if defined(__APPLE__)
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# if (defined(__POWERPC__) || defined (__ppc__) || \
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defined(_POWER) || defined(_ARCH_PPC)) || defined(__arm__)
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sys_icache_invalidate(Addr, Len);
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# endif
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#else
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# if (defined(__POWERPC__) || defined (__ppc__) || \
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defined(_POWER) || defined(_ARCH_PPC)) && defined(__GNUC__)
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const size_t LineSize = 32;
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const intptr_t Mask = ~(LineSize - 1);
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const intptr_t StartLine = ((intptr_t) Addr) & Mask;
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const intptr_t EndLine = ((intptr_t) Addr + Len + LineSize - 1) & Mask;
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for (intptr_t Line = StartLine; Line < EndLine; Line += LineSize)
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asm volatile("dcbf 0, %0" : : "r"(Line));
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asm volatile("sync");
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for (intptr_t Line = StartLine; Line < EndLine; Line += LineSize)
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asm volatile("icbi 0, %0" : : "r"(Line));
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asm volatile("isync");
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# elif defined(__arm__) && defined(__GNUC__)
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// FIXME: Can we safely always call this for __GNUC__ everywhere?
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char *Start = (char*) Addr;
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char *End = Start + Len;
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__clear_cache(Start, End);
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# elif defined(__mips__)
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ClearMipsCache(Addr, Len);
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# endif
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#endif // end apple
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ValgrindDiscardTranslations(Addr, Len);
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}
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