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91aac1015e
with an earlyclobber operand elsewhere. Propagate this bit and the earlyclobber bit through SDISel. Change linear-scan RA not to allocate regs in a way that conflicts with an earlyclobber. See also comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56290 91177308-0d34-0410-b5e6-96231b3b80d8
500 lines
20 KiB
C++
500 lines
20 KiB
C++
//===-- LiveIntervalAnalysis.h - Live Interval Analysis ---------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the LiveInterval analysis pass. Given some numbering of
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// each the machine instructions (in this implemention depth-first order) an
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// interval [i, j) is said to be a live interval for register v if there is no
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// instruction with number j' > j such that v is live at j' and there is no
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// instruction with number i' < i such that v is live at i'. In this
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// implementation intervals can have holes, i.e. an interval might look like
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// [1,20), [50,65), [1000,1001).
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
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#define LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/LiveInterval.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/Support/Allocator.h"
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#include <cmath>
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#include <map>
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namespace llvm {
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class AliasAnalysis;
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class LiveVariables;
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class MachineLoopInfo;
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class TargetRegisterInfo;
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class MachineRegisterInfo;
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class TargetInstrInfo;
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class TargetRegisterClass;
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class VirtRegMap;
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typedef std::pair<unsigned, MachineBasicBlock*> IdxMBBPair;
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inline bool operator<(unsigned V, const IdxMBBPair &IM) {
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return V < IM.first;
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}
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inline bool operator<(const IdxMBBPair &IM, unsigned V) {
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return IM.first < V;
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}
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struct Idx2MBBCompare {
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bool operator()(const IdxMBBPair &LHS, const IdxMBBPair &RHS) const {
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return LHS.first < RHS.first;
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}
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};
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class LiveIntervals : public MachineFunctionPass {
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MachineFunction* mf_;
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MachineRegisterInfo* mri_;
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const TargetMachine* tm_;
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const TargetRegisterInfo* tri_;
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const TargetInstrInfo* tii_;
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AliasAnalysis *aa_;
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LiveVariables* lv_;
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/// AsmsWithEarlyClobber - maps a virtual register number to all the
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/// inline asm's that have the register marked earlyclobber.
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///
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std::multimap<unsigned, MachineInstr*> AsmsThatEarlyClobber;
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/// AsmsWithEarlyClobberConflict - maps a virtual register number
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/// to all the inline asm's that have earlyclobber operands elsewhere
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/// and use the register as a (non-earlyclobber) input.
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///
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/// Note: earlyclobber operands may not be assigned the same register as
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/// each other, or as earlyclobber-conflict operands. However two
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/// earlyclobber-conflict operands may be assigned the same register if
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/// they happen to contain the same value.
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///
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std::multimap<unsigned, MachineInstr*> AsmsWithEarlyClobberConflict;
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/// Special pool allocator for VNInfo's (LiveInterval val#).
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///
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BumpPtrAllocator VNInfoAllocator;
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/// MBB2IdxMap - The indexes of the first and last instructions in the
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/// specified basic block.
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std::vector<std::pair<unsigned, unsigned> > MBB2IdxMap;
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/// Idx2MBBMap - Sorted list of pairs of index of first instruction
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/// and MBB id.
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std::vector<IdxMBBPair> Idx2MBBMap;
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/// FunctionSize - The number of instructions present in the function
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uint64_t FunctionSize;
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typedef DenseMap<MachineInstr*, unsigned> Mi2IndexMap;
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Mi2IndexMap mi2iMap_;
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typedef std::vector<MachineInstr*> Index2MiMap;
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Index2MiMap i2miMap_;
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typedef DenseMap<unsigned, LiveInterval*> Reg2IntervalMap;
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Reg2IntervalMap r2iMap_;
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BitVector allocatableRegs_;
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std::vector<MachineInstr*> ClonedMIs;
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public:
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static char ID; // Pass identification, replacement for typeid
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LiveIntervals() : MachineFunctionPass(&ID) {}
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struct InstrSlots {
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enum {
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LOAD = 0,
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USE = 1,
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DEF = 2,
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STORE = 3,
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NUM = 4
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};
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};
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static unsigned getBaseIndex(unsigned index) {
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return index - (index % InstrSlots::NUM);
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}
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static unsigned getBoundaryIndex(unsigned index) {
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return getBaseIndex(index + InstrSlots::NUM - 1);
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}
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static unsigned getLoadIndex(unsigned index) {
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return getBaseIndex(index) + InstrSlots::LOAD;
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}
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static unsigned getUseIndex(unsigned index) {
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return getBaseIndex(index) + InstrSlots::USE;
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}
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static unsigned getDefIndex(unsigned index) {
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return getBaseIndex(index) + InstrSlots::DEF;
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}
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static unsigned getStoreIndex(unsigned index) {
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return getBaseIndex(index) + InstrSlots::STORE;
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}
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static float getSpillWeight(bool isDef, bool isUse, unsigned loopDepth) {
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return (isDef + isUse) * powf(10.0F, (float)loopDepth);
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}
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typedef Reg2IntervalMap::iterator iterator;
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typedef Reg2IntervalMap::const_iterator const_iterator;
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const_iterator begin() const { return r2iMap_.begin(); }
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const_iterator end() const { return r2iMap_.end(); }
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iterator begin() { return r2iMap_.begin(); }
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iterator end() { return r2iMap_.end(); }
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unsigned getNumIntervals() const { return (unsigned)r2iMap_.size(); }
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LiveInterval &getInterval(unsigned reg) {
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Reg2IntervalMap::iterator I = r2iMap_.find(reg);
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assert(I != r2iMap_.end() && "Interval does not exist for register");
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return *I->second;
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}
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const LiveInterval &getInterval(unsigned reg) const {
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Reg2IntervalMap::const_iterator I = r2iMap_.find(reg);
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assert(I != r2iMap_.end() && "Interval does not exist for register");
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return *I->second;
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}
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bool hasInterval(unsigned reg) const {
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return r2iMap_.count(reg);
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}
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/// getMBBStartIdx - Return the base index of the first instruction in the
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/// specified MachineBasicBlock.
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unsigned getMBBStartIdx(MachineBasicBlock *MBB) const {
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return getMBBStartIdx(MBB->getNumber());
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}
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unsigned getMBBStartIdx(unsigned MBBNo) const {
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assert(MBBNo < MBB2IdxMap.size() && "Invalid MBB number!");
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return MBB2IdxMap[MBBNo].first;
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}
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/// getMBBEndIdx - Return the store index of the last instruction in the
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/// specified MachineBasicBlock.
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unsigned getMBBEndIdx(MachineBasicBlock *MBB) const {
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return getMBBEndIdx(MBB->getNumber());
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}
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unsigned getMBBEndIdx(unsigned MBBNo) const {
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assert(MBBNo < MBB2IdxMap.size() && "Invalid MBB number!");
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return MBB2IdxMap[MBBNo].second;
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}
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/// getScaledIntervalSize - get the size of an interval in "units,"
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/// where every function is composed of one thousand units. This
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/// measure scales properly with empty index slots in the function.
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double getScaledIntervalSize(LiveInterval& I) {
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return (1000.0 / InstrSlots::NUM * I.getSize()) / i2miMap_.size();
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}
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/// getApproximateInstructionCount - computes an estimate of the number
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/// of instructions in a given LiveInterval.
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unsigned getApproximateInstructionCount(LiveInterval& I) {
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double IntervalPercentage = getScaledIntervalSize(I) / 1000.0;
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return (unsigned)(IntervalPercentage * FunctionSize);
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}
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/// getMBBFromIndex - given an index in any instruction of an
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/// MBB return a pointer the MBB
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MachineBasicBlock* getMBBFromIndex(unsigned index) const {
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std::vector<IdxMBBPair>::const_iterator I =
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std::lower_bound(Idx2MBBMap.begin(), Idx2MBBMap.end(), index);
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// Take the pair containing the index
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std::vector<IdxMBBPair>::const_iterator J =
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((I != Idx2MBBMap.end() && I->first > index) ||
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(I == Idx2MBBMap.end() && Idx2MBBMap.size()>0)) ? (I-1): I;
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assert(J != Idx2MBBMap.end() && J->first < index+1 &&
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index <= getMBBEndIdx(J->second) &&
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"index does not correspond to an MBB");
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return J->second;
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}
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/// getInstructionIndex - returns the base index of instr
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unsigned getInstructionIndex(MachineInstr* instr) const {
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Mi2IndexMap::const_iterator it = mi2iMap_.find(instr);
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assert(it != mi2iMap_.end() && "Invalid instruction!");
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return it->second;
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}
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/// getInstructionFromIndex - given an index in any slot of an
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/// instruction return a pointer the instruction
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MachineInstr* getInstructionFromIndex(unsigned index) const {
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index /= InstrSlots::NUM; // convert index to vector index
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assert(index < i2miMap_.size() &&
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"index does not correspond to an instruction");
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return i2miMap_[index];
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}
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/// conflictsWithPhysRegDef - Returns true if the specified register
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/// is defined during the duration of the specified interval.
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bool conflictsWithPhysRegDef(const LiveInterval &li, VirtRegMap &vrm,
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unsigned reg);
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/// findLiveInMBBs - Given a live range, if the value of the range
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/// is live in any MBB returns true as well as the list of basic blocks
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/// in which the value is live.
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bool findLiveInMBBs(const LiveRange &LR,
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SmallVectorImpl<MachineBasicBlock*> &MBBs) const;
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// Interval creation
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LiveInterval &getOrCreateInterval(unsigned reg) {
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Reg2IntervalMap::iterator I = r2iMap_.find(reg);
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if (I == r2iMap_.end())
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I = r2iMap_.insert(std::make_pair(reg, createInterval(reg))).first;
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return *I->second;
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}
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/// addLiveRangeToEndOfBlock - Given a register and an instruction,
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/// adds a live range from that instruction to the end of its MBB.
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LiveRange addLiveRangeToEndOfBlock(unsigned reg,
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MachineInstr* startInst);
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// Interval removal
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void removeInterval(unsigned Reg) {
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DenseMap<unsigned, LiveInterval*>::iterator I = r2iMap_.find(Reg);
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delete I->second;
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r2iMap_.erase(I);
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}
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/// isRemoved - returns true if the specified machine instr has been
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/// removed.
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bool isRemoved(MachineInstr* instr) const {
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return !mi2iMap_.count(instr);
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}
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/// RemoveMachineInstrFromMaps - This marks the specified machine instr as
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/// deleted.
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void RemoveMachineInstrFromMaps(MachineInstr *MI) {
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// remove index -> MachineInstr and
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// MachineInstr -> index mappings
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Mi2IndexMap::iterator mi2i = mi2iMap_.find(MI);
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if (mi2i != mi2iMap_.end()) {
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i2miMap_[mi2i->second/InstrSlots::NUM] = 0;
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mi2iMap_.erase(mi2i);
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}
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}
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/// ReplaceMachineInstrInMaps - Replacing a machine instr with a new one in
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/// maps used by register allocator.
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void ReplaceMachineInstrInMaps(MachineInstr *MI, MachineInstr *NewMI) {
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Mi2IndexMap::iterator mi2i = mi2iMap_.find(MI);
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if (mi2i == mi2iMap_.end())
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return;
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i2miMap_[mi2i->second/InstrSlots::NUM] = NewMI;
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Mi2IndexMap::iterator it = mi2iMap_.find(MI);
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assert(it != mi2iMap_.end() && "Invalid instruction!");
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unsigned Index = it->second;
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mi2iMap_.erase(it);
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mi2iMap_[NewMI] = Index;
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}
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BumpPtrAllocator& getVNInfoAllocator() { return VNInfoAllocator; }
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/// getVNInfoSourceReg - Helper function that parses the specified VNInfo
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/// copy field and returns the source register that defines it.
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unsigned getVNInfoSourceReg(const VNInfo *VNI) const;
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virtual void getAnalysisUsage(AnalysisUsage &AU) const;
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virtual void releaseMemory();
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/// runOnMachineFunction - pass entry point
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virtual bool runOnMachineFunction(MachineFunction&);
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/// print - Implement the dump method.
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virtual void print(std::ostream &O, const Module* = 0) const;
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void print(std::ostream *O, const Module* M = 0) const {
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if (O) print(*O, M);
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}
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/// addIntervalsForSpills - Create new intervals for spilled defs / uses of
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/// the given interval. FIXME: It also returns the weight of the spill slot
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/// (if any is created) by reference. This is temporary.
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std::vector<LiveInterval*>
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addIntervalsForSpills(const LiveInterval& i,
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const MachineLoopInfo *loopInfo, VirtRegMap& vrm,
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float &SSWeight);
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/// addIntervalsForSpillsFast - Quickly create new intervals for spilled
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/// defs / uses without remat or splitting.
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std::vector<LiveInterval*>
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addIntervalsForSpillsFast(const LiveInterval &li,
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const MachineLoopInfo *loopInfo,
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VirtRegMap &vrm, float& SSWeight);
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/// spillPhysRegAroundRegDefsUses - Spill the specified physical register
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/// around all defs and uses of the specified interval.
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void spillPhysRegAroundRegDefsUses(const LiveInterval &li,
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unsigned PhysReg, VirtRegMap &vrm);
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/// isReMaterializable - Returns true if every definition of MI of every
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/// val# of the specified interval is re-materializable. Also returns true
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/// by reference if all of the defs are load instructions.
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bool isReMaterializable(const LiveInterval &li, bool &isLoad);
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/// getRepresentativeReg - Find the largest super register of the specified
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/// physical register.
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unsigned getRepresentativeReg(unsigned Reg) const;
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/// getNumConflictsWithPhysReg - Return the number of uses and defs of the
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/// specified interval that conflicts with the specified physical register.
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unsigned getNumConflictsWithPhysReg(const LiveInterval &li,
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unsigned PhysReg) const;
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/// noEarlyclobberConflict - see whether virtual reg VReg has a conflict
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/// with hard reg HReg because HReg is used as an earlyclobber register in
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/// asm that also has VReg live into or across it.
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bool noEarlyclobberConflict(unsigned VReg, VirtRegMap &vrm, unsigned HReg);
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/// computeNumbering - Compute the index numbering.
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void computeNumbering();
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private:
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/// computeIntervals - Compute live intervals.
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void computeIntervals();
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/// handleRegisterDef - update intervals for a register def
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/// (calls handlePhysicalRegisterDef and
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/// handleVirtualRegisterDef)
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void handleRegisterDef(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator MI, unsigned MIIdx,
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MachineOperand& MO, unsigned MOIdx);
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/// handleVirtualRegisterDef - update intervals for a virtual
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/// register def
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void handleVirtualRegisterDef(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator MI,
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unsigned MIIdx, MachineOperand& MO,
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unsigned MOIdx, LiveInterval& interval);
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/// handlePhysicalRegisterDef - update intervals for a physical register
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/// def.
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void handlePhysicalRegisterDef(MachineBasicBlock* mbb,
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MachineBasicBlock::iterator mi,
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unsigned MIIdx, MachineOperand& MO,
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LiveInterval &interval,
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MachineInstr *CopyMI);
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/// handleLiveInRegister - Create interval for a livein register.
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void handleLiveInRegister(MachineBasicBlock* mbb,
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unsigned MIIdx,
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LiveInterval &interval, bool isAlias = false);
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/// getReMatImplicitUse - If the remat definition MI has one (for now, we
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/// only allow one) virtual register operand, then its uses are implicitly
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/// using the register. Returns the virtual register.
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unsigned getReMatImplicitUse(const LiveInterval &li,
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MachineInstr *MI) const;
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/// isValNoAvailableAt - Return true if the val# of the specified interval
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/// which reaches the given instruction also reaches the specified use
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/// index.
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bool isValNoAvailableAt(const LiveInterval &li, MachineInstr *MI,
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unsigned UseIdx) const;
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/// isReMaterializable - Returns true if the definition MI of the specified
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/// val# of the specified interval is re-materializable. Also returns true
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/// by reference if the def is a load.
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bool isReMaterializable(const LiveInterval &li, const VNInfo *ValNo,
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MachineInstr *MI, bool &isLoad);
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/// tryFoldMemoryOperand - Attempts to fold either a spill / restore from
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/// slot / to reg or any rematerialized load into ith operand of specified
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/// MI. If it is successul, MI is updated with the newly created MI and
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/// returns true.
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bool tryFoldMemoryOperand(MachineInstr* &MI, VirtRegMap &vrm,
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MachineInstr *DefMI, unsigned InstrIdx,
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SmallVector<unsigned, 2> &Ops,
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bool isSS, int Slot, unsigned Reg);
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/// canFoldMemoryOperand - Return true if the specified load / store
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/// folding is possible.
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bool canFoldMemoryOperand(MachineInstr *MI,
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SmallVector<unsigned, 2> &Ops,
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bool ReMatLoadSS) const;
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/// anyKillInMBBAfterIdx - Returns true if there is a kill of the specified
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/// VNInfo that's after the specified index but is within the basic block.
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bool anyKillInMBBAfterIdx(const LiveInterval &li, const VNInfo *VNI,
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MachineBasicBlock *MBB, unsigned Idx) const;
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/// intervalIsInOneMBB - Returns true if the specified interval is entirely
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/// within a single basic block.
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bool intervalIsInOneMBB(const LiveInterval &li) const;
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/// hasAllocatableSuperReg - Return true if the specified physical register
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/// has any super register that's allocatable.
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bool hasAllocatableSuperReg(unsigned Reg) const;
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/// SRInfo - Spill / restore info.
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struct SRInfo {
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int index;
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unsigned vreg;
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bool canFold;
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SRInfo(int i, unsigned vr, bool f) : index(i), vreg(vr), canFold(f) {};
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};
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bool alsoFoldARestore(int Id, int index, unsigned vr,
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BitVector &RestoreMBBs,
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DenseMap<unsigned,std::vector<SRInfo> >&RestoreIdxes);
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void eraseRestoreInfo(int Id, int index, unsigned vr,
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BitVector &RestoreMBBs,
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DenseMap<unsigned,std::vector<SRInfo> >&RestoreIdxes);
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/// handleSpilledImpDefs - Remove IMPLICIT_DEF instructions which are being
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/// spilled and create empty intervals for their uses.
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void handleSpilledImpDefs(const LiveInterval &li, VirtRegMap &vrm,
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const TargetRegisterClass* rc,
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std::vector<LiveInterval*> &NewLIs);
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/// rewriteImplicitOps - Rewrite implicit use operands of MI (i.e. uses of
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/// interval on to-be re-materialized operands of MI) with new register.
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void rewriteImplicitOps(const LiveInterval &li,
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MachineInstr *MI, unsigned NewVReg, VirtRegMap &vrm);
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/// rewriteInstructionForSpills, rewriteInstructionsForSpills - Helper
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/// functions for addIntervalsForSpills to rewrite uses / defs for the given
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/// live range.
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bool rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI,
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bool TrySplit, unsigned index, unsigned end, MachineInstr *MI,
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MachineInstr *OrigDefMI, MachineInstr *DefMI, unsigned Slot, int LdSlot,
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bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
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VirtRegMap &vrm, const TargetRegisterClass* rc,
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SmallVector<int, 4> &ReMatIds, const MachineLoopInfo *loopInfo,
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unsigned &NewVReg, unsigned ImpUse, bool &HasDef, bool &HasUse,
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DenseMap<unsigned,unsigned> &MBBVRegsMap,
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|
std::vector<LiveInterval*> &NewLIs, float &SSWeight);
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|
void rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
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|
LiveInterval::Ranges::const_iterator &I,
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|
MachineInstr *OrigDefMI, MachineInstr *DefMI, unsigned Slot, int LdSlot,
|
|
bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
|
|
VirtRegMap &vrm, const TargetRegisterClass* rc,
|
|
SmallVector<int, 4> &ReMatIds, const MachineLoopInfo *loopInfo,
|
|
BitVector &SpillMBBs,
|
|
DenseMap<unsigned,std::vector<SRInfo> > &SpillIdxes,
|
|
BitVector &RestoreMBBs,
|
|
DenseMap<unsigned,std::vector<SRInfo> > &RestoreIdxes,
|
|
DenseMap<unsigned,unsigned> &MBBVRegsMap,
|
|
std::vector<LiveInterval*> &NewLIs, float &SSWeight);
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|
|
|
static LiveInterval* createInterval(unsigned Reg);
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|
|
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void printRegName(unsigned reg) const;
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|
};
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} // End llvm namespace
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#endif
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