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36e5511188
Some of these tests did not specify a cpu but were also sensitive to instruction scheduling and/or register assignment choices. A few others similarly-sensitive tests specified a cpu (often the POWER7), and while the P7 currently uses the default model for PPC64, this will soon change. For those tests which should not really be cpu-dependent anyway, the cpu is set to the generic 'ppc64'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195977 91177308-0d34-0410-b5e6-96231b3b80d8
22 lines
851 B
LLVM
22 lines
851 B
LLVM
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-freebsd10.0"
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; RUN: llc -O0 < %s -march=ppc64 -mcpu=ppc64 | FileCheck -check-prefix=OPT0 %s
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; RUN: llc -O1 < %s -march=ppc64 -mcpu=ppc64 | FileCheck -check-prefix=OPT1 %s
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@a = thread_local global i32 0, align 4
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;OPT0-LABEL: localexec:
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;OPT1-LABEL: localexec:
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define i32 @localexec() nounwind {
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entry:
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;OPT0: addis [[REG1:[0-9]+]], 13, a@tprel@ha
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;OPT0-NEXT: li [[REG2:[0-9]+]], 42
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;OPT0-NEXT: addi [[REG1]], [[REG1]], a@tprel@l
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;OPT0: stw [[REG2]], 0([[REG1]])
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;OPT1: addis [[REG1:[0-9]+]], 13, a@tprel@ha
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;OPT1-NEXT: li [[REG2:[0-9]+]], 42
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;OPT1-NEXT: stw [[REG2]], a@tprel@l([[REG1]])
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store i32 42, i32* @a, align 4
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ret i32 0
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}
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