mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 04:30:12 +00:00
7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
296 lines
8.7 KiB
LLVM
296 lines
8.7 KiB
LLVM
; Test 32-bit additions of constants to memory. The tests here
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; assume z10 register pressure, without the high words being available.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
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; Check additions of 1.
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define void @f1(i32 *%ptr) {
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; CHECK-LABEL: f1:
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; CHECK: asi 0(%r2), 1
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; CHECK: br %r14
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%val = load i32 , i32 *%ptr
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%add = add i32 %val, 127
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store i32 %add, i32 *%ptr
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ret void
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}
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; Check the high end of the constant range.
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define void @f2(i32 *%ptr) {
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; CHECK-LABEL: f2:
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; CHECK: asi 0(%r2), 127
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; CHECK: br %r14
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%val = load i32 , i32 *%ptr
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%add = add i32 %val, 127
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store i32 %add, i32 *%ptr
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ret void
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}
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; Check the next constant up, which must use an addition and a store.
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; Both L/AHI and LHI/A would be OK.
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define void @f3(i32 *%ptr) {
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; CHECK-LABEL: f3:
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; CHECK-NOT: asi
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; CHECK: st %r0, 0(%r2)
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; CHECK: br %r14
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%val = load i32 , i32 *%ptr
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%add = add i32 %val, 128
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store i32 %add, i32 *%ptr
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ret void
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}
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; Check the low end of the constant range.
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define void @f4(i32 *%ptr) {
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; CHECK-LABEL: f4:
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; CHECK: asi 0(%r2), -128
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; CHECK: br %r14
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%val = load i32 , i32 *%ptr
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%add = add i32 %val, -128
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store i32 %add, i32 *%ptr
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ret void
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}
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; Check the next value down, with the same comment as f3.
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define void @f5(i32 *%ptr) {
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; CHECK-LABEL: f5:
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; CHECK-NOT: asi
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; CHECK: st %r0, 0(%r2)
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; CHECK: br %r14
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%val = load i32 , i32 *%ptr
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%add = add i32 %val, -129
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store i32 %add, i32 *%ptr
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ret void
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}
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; Check the high end of the aligned ASI range.
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define void @f6(i32 *%base) {
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; CHECK-LABEL: f6:
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; CHECK: asi 524284(%r2), 1
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%base, i64 131071
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%val = load i32 , i32 *%ptr
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%add = add i32 %val, 1
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store i32 %add, i32 *%ptr
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ret void
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}
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; Check the next word up, which must use separate address logic.
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; Other sequences besides this one would be OK.
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define void @f7(i32 *%base) {
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; CHECK-LABEL: f7:
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; CHECK: agfi %r2, 524288
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; CHECK: asi 0(%r2), 1
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%base, i64 131072
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%val = load i32 , i32 *%ptr
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%add = add i32 %val, 1
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store i32 %add, i32 *%ptr
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ret void
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}
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; Check the low end of the ASI range.
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define void @f8(i32 *%base) {
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; CHECK-LABEL: f8:
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; CHECK: asi -524288(%r2), 1
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%base, i64 -131072
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%val = load i32 , i32 *%ptr
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%add = add i32 %val, 1
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store i32 %add, i32 *%ptr
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ret void
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}
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; Check the next word down, which must use separate address logic.
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; Other sequences besides this one would be OK.
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define void @f9(i32 *%base) {
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; CHECK-LABEL: f9:
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; CHECK: agfi %r2, -524292
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; CHECK: asi 0(%r2), 1
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%base, i64 -131073
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%val = load i32 , i32 *%ptr
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%add = add i32 %val, 1
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store i32 %add, i32 *%ptr
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ret void
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}
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; Check that ASI does not allow indices.
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define void @f10(i64 %base, i64 %index) {
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; CHECK-LABEL: f10:
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; CHECK: agr %r2, %r3
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; CHECK: asi 4(%r2), 1
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; CHECK: br %r14
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%add1 = add i64 %base, %index
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%add2 = add i64 %add1, 4
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%ptr = inttoptr i64 %add2 to i32 *
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%val = load i32 , i32 *%ptr
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%add = add i32 %val, 1
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store i32 %add, i32 *%ptr
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ret void
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}
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; Check that adding 127 to a spilled value can use ASI.
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define void @f11(i32 *%ptr, i32 %sel) {
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; CHECK-LABEL: f11:
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; CHECK: asi {{[0-9]+}}(%r15), 127
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; CHECK: br %r14
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entry:
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%val0 = load volatile i32 , i32 *%ptr
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%val1 = load volatile i32 , i32 *%ptr
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%val2 = load volatile i32 , i32 *%ptr
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%val3 = load volatile i32 , i32 *%ptr
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%val4 = load volatile i32 , i32 *%ptr
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%val5 = load volatile i32 , i32 *%ptr
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%val6 = load volatile i32 , i32 *%ptr
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%val7 = load volatile i32 , i32 *%ptr
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%val8 = load volatile i32 , i32 *%ptr
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%val9 = load volatile i32 , i32 *%ptr
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%val10 = load volatile i32 , i32 *%ptr
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%val11 = load volatile i32 , i32 *%ptr
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%val12 = load volatile i32 , i32 *%ptr
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%val13 = load volatile i32 , i32 *%ptr
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%val14 = load volatile i32 , i32 *%ptr
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%val15 = load volatile i32 , i32 *%ptr
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%test = icmp ne i32 %sel, 0
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br i1 %test, label %add, label %store
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add:
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%add0 = add i32 %val0, 127
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%add1 = add i32 %val1, 127
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%add2 = add i32 %val2, 127
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%add3 = add i32 %val3, 127
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%add4 = add i32 %val4, 127
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%add5 = add i32 %val5, 127
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%add6 = add i32 %val6, 127
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%add7 = add i32 %val7, 127
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%add8 = add i32 %val8, 127
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%add9 = add i32 %val9, 127
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%add10 = add i32 %val10, 127
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%add11 = add i32 %val11, 127
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%add12 = add i32 %val12, 127
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%add13 = add i32 %val13, 127
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%add14 = add i32 %val14, 127
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%add15 = add i32 %val15, 127
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br label %store
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store:
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%new0 = phi i32 [ %val0, %entry ], [ %add0, %add ]
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%new1 = phi i32 [ %val1, %entry ], [ %add1, %add ]
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%new2 = phi i32 [ %val2, %entry ], [ %add2, %add ]
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%new3 = phi i32 [ %val3, %entry ], [ %add3, %add ]
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%new4 = phi i32 [ %val4, %entry ], [ %add4, %add ]
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%new5 = phi i32 [ %val5, %entry ], [ %add5, %add ]
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%new6 = phi i32 [ %val6, %entry ], [ %add6, %add ]
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%new7 = phi i32 [ %val7, %entry ], [ %add7, %add ]
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%new8 = phi i32 [ %val8, %entry ], [ %add8, %add ]
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%new9 = phi i32 [ %val9, %entry ], [ %add9, %add ]
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%new10 = phi i32 [ %val10, %entry ], [ %add10, %add ]
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%new11 = phi i32 [ %val11, %entry ], [ %add11, %add ]
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%new12 = phi i32 [ %val12, %entry ], [ %add12, %add ]
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%new13 = phi i32 [ %val13, %entry ], [ %add13, %add ]
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%new14 = phi i32 [ %val14, %entry ], [ %add14, %add ]
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%new15 = phi i32 [ %val15, %entry ], [ %add15, %add ]
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store volatile i32 %new0, i32 *%ptr
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store volatile i32 %new1, i32 *%ptr
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store volatile i32 %new2, i32 *%ptr
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store volatile i32 %new3, i32 *%ptr
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store volatile i32 %new4, i32 *%ptr
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store volatile i32 %new5, i32 *%ptr
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store volatile i32 %new6, i32 *%ptr
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store volatile i32 %new7, i32 *%ptr
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store volatile i32 %new8, i32 *%ptr
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store volatile i32 %new9, i32 *%ptr
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store volatile i32 %new10, i32 *%ptr
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store volatile i32 %new11, i32 *%ptr
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store volatile i32 %new12, i32 *%ptr
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store volatile i32 %new13, i32 *%ptr
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store volatile i32 %new14, i32 *%ptr
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store volatile i32 %new15, i32 *%ptr
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ret void
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}
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; Check that adding -128 to a spilled value can use ASI.
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define void @f12(i32 *%ptr, i32 %sel) {
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; CHECK-LABEL: f12:
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; CHECK: asi {{[0-9]+}}(%r15), -128
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; CHECK: br %r14
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entry:
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%val0 = load volatile i32 , i32 *%ptr
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%val1 = load volatile i32 , i32 *%ptr
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%val2 = load volatile i32 , i32 *%ptr
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%val3 = load volatile i32 , i32 *%ptr
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%val4 = load volatile i32 , i32 *%ptr
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%val5 = load volatile i32 , i32 *%ptr
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%val6 = load volatile i32 , i32 *%ptr
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%val7 = load volatile i32 , i32 *%ptr
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%val8 = load volatile i32 , i32 *%ptr
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%val9 = load volatile i32 , i32 *%ptr
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%val10 = load volatile i32 , i32 *%ptr
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%val11 = load volatile i32 , i32 *%ptr
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%val12 = load volatile i32 , i32 *%ptr
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%val13 = load volatile i32 , i32 *%ptr
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%val14 = load volatile i32 , i32 *%ptr
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%val15 = load volatile i32 , i32 *%ptr
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%test = icmp ne i32 %sel, 0
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br i1 %test, label %add, label %store
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add:
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%add0 = add i32 %val0, -128
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%add1 = add i32 %val1, -128
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%add2 = add i32 %val2, -128
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%add3 = add i32 %val3, -128
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%add4 = add i32 %val4, -128
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%add5 = add i32 %val5, -128
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%add6 = add i32 %val6, -128
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%add7 = add i32 %val7, -128
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%add8 = add i32 %val8, -128
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%add9 = add i32 %val9, -128
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%add10 = add i32 %val10, -128
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%add11 = add i32 %val11, -128
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%add12 = add i32 %val12, -128
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%add13 = add i32 %val13, -128
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%add14 = add i32 %val14, -128
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%add15 = add i32 %val15, -128
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br label %store
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store:
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%new0 = phi i32 [ %val0, %entry ], [ %add0, %add ]
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%new1 = phi i32 [ %val1, %entry ], [ %add1, %add ]
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%new2 = phi i32 [ %val2, %entry ], [ %add2, %add ]
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%new3 = phi i32 [ %val3, %entry ], [ %add3, %add ]
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%new4 = phi i32 [ %val4, %entry ], [ %add4, %add ]
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%new5 = phi i32 [ %val5, %entry ], [ %add5, %add ]
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%new6 = phi i32 [ %val6, %entry ], [ %add6, %add ]
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%new7 = phi i32 [ %val7, %entry ], [ %add7, %add ]
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%new8 = phi i32 [ %val8, %entry ], [ %add8, %add ]
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%new9 = phi i32 [ %val9, %entry ], [ %add9, %add ]
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%new10 = phi i32 [ %val10, %entry ], [ %add10, %add ]
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%new11 = phi i32 [ %val11, %entry ], [ %add11, %add ]
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%new12 = phi i32 [ %val12, %entry ], [ %add12, %add ]
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%new13 = phi i32 [ %val13, %entry ], [ %add13, %add ]
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%new14 = phi i32 [ %val14, %entry ], [ %add14, %add ]
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%new15 = phi i32 [ %val15, %entry ], [ %add15, %add ]
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store volatile i32 %new0, i32 *%ptr
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store volatile i32 %new1, i32 *%ptr
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store volatile i32 %new2, i32 *%ptr
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store volatile i32 %new3, i32 *%ptr
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store volatile i32 %new4, i32 *%ptr
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store volatile i32 %new5, i32 *%ptr
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store volatile i32 %new6, i32 *%ptr
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store volatile i32 %new7, i32 *%ptr
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store volatile i32 %new8, i32 *%ptr
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store volatile i32 %new9, i32 *%ptr
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store volatile i32 %new10, i32 *%ptr
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store volatile i32 %new11, i32 *%ptr
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store volatile i32 %new12, i32 *%ptr
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store volatile i32 %new13, i32 *%ptr
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store volatile i32 %new14, i32 *%ptr
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store volatile i32 %new15, i32 *%ptr
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ret void
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}
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