Jakob Stoklund Olesen eeb57c7701 Don't check liveness of unallocatable registers. ... This includes registers like EFLAGS and ST0-ST7. We don't check for liveness issues in the verifier and scavenger because registers will never be allocated from these classes. While in SSA form, we do care about the liveness of unallocatable unreserved registers. Liveness of EFLAGS and ST0 neds to be correct for MachineDCE and MachineSinking. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136541 91177308-0d34-0410-b5e6-96231b3b80d8		2011-07-29 23:36:21 +00:00
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Alpha
ARM	Add support for the 'Q' constraint.	2011-07-29 21:18:58 +00:00
Blackfin
CBackend
CellSPU
CPP
Generic
MBlaze
Mips	Lower memory barriers to sync instructions.	2011-07-19 23:30:50 +00:00
MSP430
PowerPC	Add MCObjectFileInfo and sink the MCSections initialization code from	2011-07-20 05:58:47 +00:00
PTX
SPARC
SystemZ
Thumb
Thumb2
X86	Don't check liveness of unallocatable registers.	2011-07-29 23:36:21 +00:00
XCore	Add intrinsics for the zext / sext instructions.	2011-07-19 13:28:50 +00:00