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https://github.com/c64scene-ar/llvm-6502.git
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bf2f8a9963
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7728 91177308-0d34-0410-b5e6-96231b3b80d8
101 lines
4.0 KiB
C++
101 lines
4.0 KiB
C++
//===- X86RegisterInfo.td - Describe the X86 Register File ------*- C++ -*-===//
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//
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// This file describes the X86 Register file, defining the registers themselves,
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// aliases between the registers, and the register classes built out of the
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// registers.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Register definitions...
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//
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let Namespace = "X86" in {
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// 32-bit registers
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def EAX : Register; def ECX : Register;
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def EDX : Register; def EBX : Register;
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def ESP : Register; def EBP : Register;
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def ESI : Register; def EDI : Register;
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// 16-bit registers
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def AX : Register; def CX : Register;
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def DX : Register; def BX : Register;
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def SP : Register; def BP : Register;
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def SI : Register; def DI : Register;
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// 8-bit registers
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def AL : Register; def CL : Register;
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def DL : Register; def BL : Register;
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def AH : Register; def CH : Register;
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def DH : Register; def BH : Register;
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// Pseudo Floating Point registers
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def FP0 : Register; def FP1 : Register;
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def FP2 : Register; def FP3 : Register;
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def FP4 : Register; def FP5 : Register;
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def FP6 : Register;
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// Floating point stack registers
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def ST0 : NamedReg<"ST(0)">; def ST1 : NamedReg<"ST(1)">;
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def ST2 : NamedReg<"ST(2)">; def ST3 : NamedReg<"ST(3)">;
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def ST4 : NamedReg<"ST(4)">; def ST5 : NamedReg<"ST(5)">;
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def ST6 : NamedReg<"ST(6)">; def ST7 : NamedReg<"ST(7)">;
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// Flags, Segment registers, etc...
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// This is a slimy hack to make it possible to say that flags are clobbered...
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// Ideally we'd model instructions based on which particular flag(s) they
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// could clobber.
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//def EFLAGS : Register;
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}
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//===----------------------------------------------------------------------===//
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// Register alias definitions... define which registers alias which others. We
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// only specify which registers the small registers alias, because the register
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// file generator is smart enough to figure out that AL aliases AX if we tell it
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// that AX aliases AL (for example).
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//
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def : RegisterAliases<AL, [AX, EAX]>; def : RegisterAliases<BL, [BX, EBX]>;
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def : RegisterAliases<CL, [CX, ECX]>; def : RegisterAliases<DL, [DX, EDX]>;
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def : RegisterAliases<AH, [AX, EAX]>; def : RegisterAliases<BH, [BX, EBX]>;
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def : RegisterAliases<CH, [CX, ECX]>; def : RegisterAliases<DH, [DX, EDX]>;
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def : RegisterAliases<AX, [EAX]>; def : RegisterAliases<BX, [EBX]>;
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def : RegisterAliases<CX, [ECX]>; def : RegisterAliases<DX, [EDX]>;
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def : RegisterAliases<SI, [ESI]>; def : RegisterAliases<DI, [EDI]>;
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def : RegisterAliases<SP, [ESP]>; def : RegisterAliases<BP, [EBP]>;
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//===----------------------------------------------------------------------===//
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// Register Class Definitions... now that we have all of the pieces, define the
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// top-level register classes. The order specified in the register list is
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// implicitly defined to be the register allocation order.
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//
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def R8 : RegisterClass<i8, 1, [AL, CL, DL, BL, AH, CH, DH, BH]>;
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def R16 : RegisterClass<i16, 2, [AX, CX, DX, BX, SI, DI, BP, SP]> {
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let Methods = [{
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iterator allocation_order_end(MachineFunction &MF) const {
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if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr?
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return end()-2; // If so, don't allocate SP or BP
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else
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return end()-1; // If not, just don't allocate SP
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}
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}];
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}
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def R32 : RegisterClass<i32, 4, [EAX, ECX, EDX, EBX, ESI, EDI, EBP, ESP]> {
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let Methods = [{
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iterator allocation_order_end(MachineFunction &MF) const {
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if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr?
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return end()-2; // If so, don't allocate ESP or EBP
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else
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return end()-1; // If not, just don't allocate ESP
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}
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}];
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}
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def RFP : RegisterClass<f80, 4, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
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// Registers which cannot be allocated... and are thus left unnamed.
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def : RegisterClass<f80, 4, [ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]>;
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//def : RegisterClass<i16, 2, [EFLAGS]>;
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