Richard Osborne ef174f733a [XCore] Provide information about known zero bits of resource instructions. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202393 91177308-0d34-0410-b5e6-96231b3b80d8		2014-02-27 13:20:06 +00:00
..
AArch64	AArch64: simplify tbl/tbx polymorphism	2014-02-26 11:55:09 +00:00
ARM	Stop test/CodeGen/ARM/a15.ll targetting non-ARM targets.	2014-02-26 11:26:18 +00:00
CPP
Generic
Hexagon
Inputs
Mips
MSP430
NVPTX
PowerPC	Account for 128-bit integer operations in PPCCTRLoops	2014-02-25 20:51:50 +00:00
R600	R600/SI: Optimize SI_KILL for constant operands	2014-02-27 01:47:09 +00:00
SPARC	SPARC: Implement TRAP lowering. Matches what GCC emits.	2014-02-23 21:43:52 +00:00
SystemZ
Thumb
Thumb2	ARMv8 IfConversion must skip narrow instructions that a) define CPSR and b) wouldn't affect CPSR in an IT block	2014-02-26 11:27:28 +00:00
X86	Stop test/CodeGen/X86/v4i32load-crash.ll targeting non-X86-64 targets.	2014-02-27 09:24:31 +00:00
XCore	[XCore] Provide information about known zero bits of resource instructions.	2014-02-27 13:20:06 +00:00