Tilmann Scheller 79c163d6dd ARM: Prevent ARMAsmParser::shouldOmitCCOutOperand() from misidentifying certain Thumb2 add immediate T3 encodings. ... Before the fix Thumb2 instructions of type "add rD, rN, #imm" (T3 encoding, see ARM ARM A8.8.4) with rD and rN both being low registers (r0-r7) were classified as having the T4 encoding. The T4 encoding doesn't have a cc_out operand so for above instructions the operand gets erroneously removed, corrupting the token stream and leading to parse errors later in the process. This bug prevented "add r1, r7, #0xcbcbcbcb" from being assembled correctly. Fixes <rdar://problem/14224440>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185575 91177308-0d34-0410-b5e6-96231b3b80d8		2013-07-03 20:38:01 +00:00
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AArch64	Prefix failing commands with not to make clear they are expected to fail.	2013-07-03 16:41:29 +00:00
ARM	ARM: Prevent ARMAsmParser::shouldOmitCCOutOperand() from misidentifying certain Thumb2 add immediate T3 encodings.	2013-07-03 20:38:01 +00:00
AsmParser	Prefix failing commands with not to make clear they are expected to fail.	2013-07-03 16:41:29 +00:00
COFF
Disassembler	This corrects the implementation of Thumb ADR instruction. There are three issues:	2013-07-03 09:21:44 +00:00
ELF
MachO
Markup
MBlaze
Mips
PowerPC	[PowerPC] Support lmw/stmw in the asm parser	2013-07-03 18:29:47 +00:00
SystemZ	[SystemZ] Add the MVC instruction	2013-07-02 14:56:45 +00:00
X86	Prefix failing commands with not to make clear they are expected to fail.	2013-07-03 16:41:29 +00:00