mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-26 23:29:22 +00:00
29f94c7201
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209577 91177308-0d34-0410-b5e6-96231b3b80d8
257 lines
9.2 KiB
LLVM
257 lines
9.2 KiB
LLVM
; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
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; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP %s
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@var_8bit = global i8 0
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@var_16bit = global i16 0
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@var_32bit = global i32 0
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@var_64bit = global i64 0
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@var_float = global float 0.0
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@var_double = global double 0.0
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define void @ldst_8bit() {
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; CHECK-LABEL: ldst_8bit:
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; No architectural support for loads to 16-bit or 8-bit since we
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; promote i8 during lowering.
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; match a sign-extending load 8-bit -> 32-bit
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%val8_sext32 = load volatile i8* @var_8bit
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%val32_signed = sext i8 %val8_sext32 to i32
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store volatile i32 %val32_signed, i32* @var_32bit
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; CHECK: adrp {{x[0-9]+}}, var_8bit
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; CHECK: ldrsb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
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; match a zero-extending load volatile 8-bit -> 32-bit
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%val8_zext32 = load volatile i8* @var_8bit
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%val32_unsigned = zext i8 %val8_zext32 to i32
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store volatile i32 %val32_unsigned, i32* @var_32bit
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; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
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; match an any-extending load volatile 8-bit -> 32-bit
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%val8_anyext = load volatile i8* @var_8bit
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%newval8 = add i8 %val8_anyext, 1
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store volatile i8 %newval8, i8* @var_8bit
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; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
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; match a sign-extending load volatile 8-bit -> 64-bit
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%val8_sext64 = load volatile i8* @var_8bit
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%val64_signed = sext i8 %val8_sext64 to i64
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store volatile i64 %val64_signed, i64* @var_64bit
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; CHECK: ldrsb {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
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; match a zero-extending load volatile 8-bit -> 64-bit.
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; This uses the fact that ldrb w0, [x0] will zero out the high 32-bits
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; of x0 so it's identical to load volatileing to 32-bits.
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%val8_zext64 = load volatile i8* @var_8bit
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%val64_unsigned = zext i8 %val8_zext64 to i64
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store volatile i64 %val64_unsigned, i64* @var_64bit
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; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
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; truncating store volatile 32-bits to 8-bits
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%val32 = load volatile i32* @var_32bit
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%val8_trunc32 = trunc i32 %val32 to i8
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store volatile i8 %val8_trunc32, i8* @var_8bit
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; CHECK: strb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
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; truncating store volatile 64-bits to 8-bits
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%val64 = load volatile i64* @var_64bit
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%val8_trunc64 = trunc i64 %val64 to i8
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store volatile i8 %val8_trunc64, i8* @var_8bit
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; CHECK: strb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
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ret void
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}
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define void @ldst_16bit() {
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; CHECK-LABEL: ldst_16bit:
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; No architectural support for load volatiles to 16-bit promote i16 during
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; lowering.
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; match a sign-extending load volatile 16-bit -> 32-bit
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%val16_sext32 = load volatile i16* @var_16bit
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%val32_signed = sext i16 %val16_sext32 to i32
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store volatile i32 %val32_signed, i32* @var_32bit
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; CHECK: adrp {{x[0-9]+}}, var_16bit
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; CHECK: ldrsh {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_16bit]
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; match a zero-extending load volatile 16-bit -> 32-bit
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%val16_zext32 = load volatile i16* @var_16bit
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%val32_unsigned = zext i16 %val16_zext32 to i32
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store volatile i32 %val32_unsigned, i32* @var_32bit
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; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_16bit]
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; match an any-extending load volatile 16-bit -> 32-bit
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%val16_anyext = load volatile i16* @var_16bit
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%newval16 = add i16 %val16_anyext, 1
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store volatile i16 %newval16, i16* @var_16bit
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; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_16bit]
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; match a sign-extending load volatile 16-bit -> 64-bit
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%val16_sext64 = load volatile i16* @var_16bit
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%val64_signed = sext i16 %val16_sext64 to i64
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store volatile i64 %val64_signed, i64* @var_64bit
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; CHECK: ldrsh {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_16bit]
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; match a zero-extending load volatile 16-bit -> 64-bit.
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; This uses the fact that ldrb w0, [x0] will zero out the high 32-bits
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; of x0 so it's identical to load volatileing to 32-bits.
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%val16_zext64 = load volatile i16* @var_16bit
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%val64_unsigned = zext i16 %val16_zext64 to i64
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store volatile i64 %val64_unsigned, i64* @var_64bit
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; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_16bit]
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; truncating store volatile 32-bits to 16-bits
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%val32 = load volatile i32* @var_32bit
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%val16_trunc32 = trunc i32 %val32 to i16
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store volatile i16 %val16_trunc32, i16* @var_16bit
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; CHECK: strh {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_16bit]
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; truncating store volatile 64-bits to 16-bits
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%val64 = load volatile i64* @var_64bit
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%val16_trunc64 = trunc i64 %val64 to i16
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store volatile i16 %val16_trunc64, i16* @var_16bit
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; CHECK: strh {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_16bit]
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ret void
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}
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define void @ldst_32bit() {
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; CHECK-LABEL: ldst_32bit:
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; Straight 32-bit load/store
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%val32_noext = load volatile i32* @var_32bit
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store volatile i32 %val32_noext, i32* @var_32bit
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; CHECK: adrp {{x[0-9]+}}, var_32bit
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; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_32bit]
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; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_32bit]
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; Zero-extension to 64-bits
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%val32_zext = load volatile i32* @var_32bit
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%val64_unsigned = zext i32 %val32_zext to i64
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store volatile i64 %val64_unsigned, i64* @var_64bit
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; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_32bit]
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; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_64bit]
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; Sign-extension to 64-bits
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%val32_sext = load volatile i32* @var_32bit
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%val64_signed = sext i32 %val32_sext to i64
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store volatile i64 %val64_signed, i64* @var_64bit
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; CHECK: ldrsw {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_32bit]
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; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_64bit]
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; Truncation from 64-bits
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%val64_trunc = load volatile i64* @var_64bit
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%val32_trunc = trunc i64 %val64_trunc to i32
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store volatile i32 %val32_trunc, i32* @var_32bit
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; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_64bit]
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; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_32bit]
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ret void
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}
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@arr8 = global i8* null
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@arr16 = global i16* null
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@arr32 = global i32* null
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@arr64 = global i64* null
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; Now check that our selection copes with accesses more complex than a
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; single symbol. Permitted offsets should be folded into the loads and
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; stores. Since all forms use the same Operand it's only necessary to
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; check the various access-sizes involved.
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define void @ldst_complex_offsets() {
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; CHECK: ldst_complex_offsets
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%arr8_addr = load volatile i8** @arr8
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; CHECK: adrp {{x[0-9]+}}, arr8
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; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:arr8]
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%arr8_sub1_addr = getelementptr i8* %arr8_addr, i64 1
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%arr8_sub1 = load volatile i8* %arr8_sub1_addr
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store volatile i8 %arr8_sub1, i8* @var_8bit
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; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, #1]
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%arr8_sub4095_addr = getelementptr i8* %arr8_addr, i64 4095
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%arr8_sub4095 = load volatile i8* %arr8_sub4095_addr
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store volatile i8 %arr8_sub4095, i8* @var_8bit
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; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, #4095]
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%arr16_addr = load volatile i16** @arr16
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; CHECK: adrp {{x[0-9]+}}, arr16
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; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:arr16]
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%arr16_sub1_addr = getelementptr i16* %arr16_addr, i64 1
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%arr16_sub1 = load volatile i16* %arr16_sub1_addr
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store volatile i16 %arr16_sub1, i16* @var_16bit
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; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, #2]
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%arr16_sub4095_addr = getelementptr i16* %arr16_addr, i64 4095
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%arr16_sub4095 = load volatile i16* %arr16_sub4095_addr
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store volatile i16 %arr16_sub4095, i16* @var_16bit
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; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, #8190]
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%arr32_addr = load volatile i32** @arr32
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; CHECK: adrp {{x[0-9]+}}, arr32
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; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:arr32]
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%arr32_sub1_addr = getelementptr i32* %arr32_addr, i64 1
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%arr32_sub1 = load volatile i32* %arr32_sub1_addr
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store volatile i32 %arr32_sub1, i32* @var_32bit
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; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, #4]
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%arr32_sub4095_addr = getelementptr i32* %arr32_addr, i64 4095
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%arr32_sub4095 = load volatile i32* %arr32_sub4095_addr
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store volatile i32 %arr32_sub4095, i32* @var_32bit
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; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, #16380]
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%arr64_addr = load volatile i64** @arr64
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; CHECK: adrp {{x[0-9]+}}, arr64
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; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:arr64]
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%arr64_sub1_addr = getelementptr i64* %arr64_addr, i64 1
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%arr64_sub1 = load volatile i64* %arr64_sub1_addr
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store volatile i64 %arr64_sub1, i64* @var_64bit
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; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, #8]
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%arr64_sub4095_addr = getelementptr i64* %arr64_addr, i64 4095
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%arr64_sub4095 = load volatile i64* %arr64_sub4095_addr
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store volatile i64 %arr64_sub4095, i64* @var_64bit
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; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, #32760]
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ret void
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}
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define void @ldst_float() {
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; CHECK-LABEL: ldst_float:
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%valfp = load volatile float* @var_float
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; CHECK: adrp {{x[0-9]+}}, var_float
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; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_float]
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; CHECK-NOFP-NOT: ldr {{s[0-9]+}},
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store volatile float %valfp, float* @var_float
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; CHECK: str {{s[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_float]
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; CHECK-NOFP-NOT: str {{s[0-9]+}},
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ret void
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}
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define void @ldst_double() {
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; CHECK-LABEL: ldst_double:
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%valfp = load volatile double* @var_double
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; CHECK: adrp {{x[0-9]+}}, var_double
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; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_double]
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; CHECK-NOFP-NOT: ldr {{d[0-9]+}},
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store volatile double %valfp, double* @var_double
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; CHECK: str {{d[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_double]
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; CHECK-NOFP-NOT: str {{d[0-9]+}},
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ret void
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}
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