Craig Topper 8e121843c1 Add disassembler support for SSE4.1 register/register form of PEXTRW. There is a shorter encoding that was part of SSE2, but a memory form was added in SSE4.1. This is the register form of that encoding. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192566 91177308-0d34-0410-b5e6-96231b3b80d8		2013-10-14 01:42:32 +00:00
..
hex-immediates.txt
intel-syntax-32.txt	First round of fixes for the x86 fixes for the x86 move accumulator from/to memory offset instructions.	2013-08-25 22:23:38 +00:00
intel-syntax.txt	Fixing Intel format of the vshufpd instruction.	2013-09-27 01:44:23 +00:00
invalid-cmp-imm.txt
invalid-VEX-vvvv.txt
lit.local.cfg	[tests] Cleanup initialization of test suffixes.	2013-08-16 00:37:11 +00:00
marked-up.txt
prefixes.txt	Fixed a bug where diassembling an instruction that had a prefix would cause LLVM to identify a 1-byte instruction, but then upon querying it for that 1-byte instruction would cause an undefined opcode.	2013-08-30 21:19:48 +00:00
simple-tests.txt	Add XOP disassembler support. Fixes PR13933.	2013-10-03 05:17:48 +00:00
truncated-input.txt
x86-32.txt	Remove some instructions that seem to only exist to trick the filtering checks in the disassembler table creation. Just fix up the filter to let the real instruction through instead.	2013-10-07 07:19:47 +00:00
x86-64.txt	Add disassembler support for SSE4.1 register/register form of PEXTRW. There is a shorter encoding that was part of SSE2, but a memory form was added in SSE4.1. This is the register form of that encoding.	2013-10-14 01:42:32 +00:00