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https://github.com/c64scene-ar/llvm-6502.git
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df2e425f2a
not spending tons of time microoptimizing it. This is useful for an -O0 style of build. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24235 91177308-0d34-0410-b5e6-96231b3b80d8
175 lines
5.6 KiB
C++
175 lines
5.6 KiB
C++
//===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Top-level implementation for the PowerPC target.
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//
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//===----------------------------------------------------------------------===//
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#include "PPC.h"
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#include "PPCFrameInfo.h"
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#include "PPCTargetMachine.h"
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#include "PPCJITInfo.h"
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#include "llvm/Module.h"
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#include "llvm/PassManager.h"
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#include "llvm/Analysis/Verifier.h"
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#include "llvm/CodeGen/IntrinsicLowering.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetMachineRegistry.h"
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#include "llvm/Transforms/Scalar.h"
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#include "llvm/Support/CommandLine.h"
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#include <iostream>
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using namespace llvm;
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namespace {
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static cl::opt<bool> DisablePPCDAGDAG("disable-ppc-dag-isel", cl::Hidden,
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cl::desc("Disable DAG-to-DAG isel for PPC"));
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// Register the targets
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RegisterTarget<PPCTargetMachine>
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X("ppc32", " PowerPC");
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}
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unsigned PPCTargetMachine::getJITMatchQuality() {
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#if defined(__POWERPC__) || defined (__ppc__) || defined(_POWER)
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return 10;
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#else
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return 0;
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#endif
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}
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unsigned PPCTargetMachine::getModuleMatchQuality(const Module &M) {
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// We strongly match "powerpc-*".
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std::string TT = M.getTargetTriple();
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if (TT.size() >= 8 && std::string(TT.begin(), TT.begin()+8) == "powerpc-")
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return 20;
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if (M.getEndianness() == Module::BigEndian &&
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M.getPointerSize() == Module::Pointer32)
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return 10; // Weak match
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else if (M.getEndianness() != Module::AnyEndianness ||
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M.getPointerSize() != Module::AnyPointerSize)
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return 0; // Match for some other target
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return getJITMatchQuality()/2;
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}
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PPCTargetMachine::PPCTargetMachine(const Module &M, IntrinsicLowering *IL,
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const std::string &FS)
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: TargetMachine("PowerPC", IL, false, 4, 4, 4, 4, 4, 4, 2, 1, 1),
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Subtarget(M, FS), FrameInfo(*this, false), JITInfo(*this),
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InstrItins(Subtarget.getInstrItineraryData()) {
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if (TargetDefault == PPCTarget) {
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if (Subtarget.isAIX()) PPCTarget = TargetAIX;
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if (Subtarget.isDarwin()) PPCTarget = TargetDarwin;
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}
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}
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/// addPassesToEmitFile - Add passes to the specified pass manager to implement
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/// a static compiler for this target.
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///
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bool PPCTargetMachine::addPassesToEmitFile(PassManager &PM,
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std::ostream &Out,
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CodeGenFileType FileType,
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bool Fast) {
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if (FileType != TargetMachine::AssemblyFile) return true;
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// Run loop strength reduction before anything else.
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if (!Fast) PM.add(createLoopStrengthReducePass());
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// FIXME: Implement efficient support for garbage collection intrinsics.
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PM.add(createLowerGCPass());
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// FIXME: Implement the invoke/unwind instructions!
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PM.add(createLowerInvokePass());
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// Clean up after other passes, e.g. merging critical edges.
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if (!Fast) PM.add(createCFGSimplificationPass());
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// FIXME: Implement the switch instruction in the instruction selector!
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PM.add(createLowerSwitchPass());
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// Make sure that no unreachable blocks are instruction selected.
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PM.add(createUnreachableBlockEliminationPass());
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// Install an instruction selector.
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if (!DisablePPCDAGDAG)
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PM.add(createPPCISelDag(*this));
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else
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PM.add(createPPCISelPattern(*this));
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(&std::cerr));
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PM.add(createRegisterAllocator());
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(&std::cerr));
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PM.add(createPrologEpilogCodeInserter());
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// Must run branch selection immediately preceding the asm printer
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PM.add(createPPCBranchSelectionPass());
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// Decide which asm printer to use. If the user has not specified one on
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// the command line, choose whichever one matches the default (current host).
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switch (PPCTarget) {
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case TargetAIX:
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PM.add(createAIXAsmPrinter(Out, *this));
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break;
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case TargetDefault:
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case TargetDarwin:
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PM.add(createDarwinAsmPrinter(Out, *this));
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break;
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}
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PM.add(createMachineCodeDeleter());
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return false;
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}
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void PPCJITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
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// The JIT does not support or need PIC.
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PICEnabled = false;
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// Run loop strength reduction before anything else.
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PM.add(createLoopStrengthReducePass());
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// FIXME: Implement efficient support for garbage collection intrinsics.
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PM.add(createLowerGCPass());
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// FIXME: Implement the invoke/unwind instructions!
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PM.add(createLowerInvokePass());
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// Clean up after other passes, e.g. merging critical edges.
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PM.add(createCFGSimplificationPass());
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// FIXME: Implement the switch instruction in the instruction selector!
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PM.add(createLowerSwitchPass());
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// Make sure that no unreachable blocks are instruction selected.
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PM.add(createUnreachableBlockEliminationPass());
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// Install an instruction selector.
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if (!DisablePPCDAGDAG)
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PM.add(createPPCISelDag(TM));
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else
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PM.add(createPPCISelPattern(TM));
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PM.add(createRegisterAllocator());
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PM.add(createPrologEpilogCodeInserter());
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// Must run branch selection immediately preceding the asm printer
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PM.add(createPPCBranchSelectionPass());
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(&std::cerr));
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}
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