llvm-6502/test/CodeGen
Dan Gohman ef74e9bf2a Fix an x86 code size regression: prefer RIP-relative addressing
over absolute addressing even in non-PIC mode (unless the address
has an index or something else incompatible), because it has a
smaller encoding.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79553 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-20 18:23:44 +00:00
..
Alpha
ARM Add support for Neon VEXT (vector extract) shuffles. 2009-08-19 17:03:43 +00:00
Blackfin Add XFAIL testcase for setcc undef. 2009-08-15 12:10:22 +00:00
CBackend
CellSPU
CPP
Generic
Mips reintroduce support for Mips "small" section handling. This is 2009-08-13 06:28:06 +00:00
MSP430
PIC16 this passes. 2009-08-06 03:55:49 +00:00
PowerPC PowerPC inline asm was emitting two output operands 2009-08-18 00:18:39 +00:00
SPARC
SystemZ Various AsmWriter output cleanups. Use WriteAsOperand instead of 2009-08-13 01:36:44 +00:00
Thumb Fix an obvious copy-n-paste bug. 2009-08-20 17:01:04 +00:00
Thumb2 Make tail merging handle blocks with repeated predecessors correctly, and 2009-08-18 15:18:18 +00:00
X86 Fix an x86 code size regression: prefer RIP-relative addressing 2009-08-20 18:23:44 +00:00
XCore Add support for mergeable sections back into the XCore backend. 2009-08-18 21:14:31 +00:00