Hal Finkel 341c1a50ad Actually fix PPC64 64-bit GPR inline asm constraint matching ... This is a follow-up to r187693, correcting that code to request the correct register class. The previous version, with the wrong register class, was not really correcting the constraints, but rather was removing them. Coincidentally, this fixed the failing test case in r187693, but obviously created other problems. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188407 91177308-0d34-0410-b5e6-96231b3b80d8		2013-08-14 20:05:04 +00:00
..
AArch64	CHECK-LABEL-ify tests	2013-08-09 17:50:15 +00:00
ARM	Let t2LDRBi8 and t2LDRBi12 have same Base Pointer	2013-08-14 16:35:29 +00:00
CPP
Generic
Hexagon	Refactor isInTailCallPosition handling	2013-08-06 09:12:35 +00:00
Inputs
Mips	[mips] Properly parse registers that appear in inline-asm constraints.	2013-08-14 00:21:25 +00:00
MSP430
NVPTX	[NVPTX] Add missing patterns for i1 [s,u]int_to_fp	2013-08-06 14:13:34 +00:00
PowerPC	Actually fix PPC64 64-bit GPR inline asm constraint matching	2013-08-14 20:05:04 +00:00
R600	R600: Set scheduling preference to Sched::Source	2013-08-12 22:33:21 +00:00
SI
SPARC
SystemZ	[SystemZ] Use CLC and IPM to implement memcmp	2013-08-12 10:28:10 +00:00
Thumb
Thumb2
X86	llvm/test/CodeGen/X86/setcc-sentinals.ll: Relax expressions for x86_64-win32.	2013-08-14 00:46:00 +00:00
XCore	XCore target: Fix Vararg handling	2013-08-01 08:29:44 +00:00