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https://github.com/c64scene-ar/llvm-6502.git
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9568e5c3c3
1. (((x) & 0xFF00) >> 8) | (((x) & 0x00FF) << 8) => (bswap x) >> 16 2. ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0xff000000)>>8)|((x&0x00ff0000)<<8)) => (rotl (bswap x) 16) This allows us to eliminate most of the def : Pat patterns for ARM rev16 revsh instructions. It catches many more cases for ARM and x86. rdar://9609108 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133503 91177308-0d34-0410-b5e6-96231b3b80d8
60 lines
1.2 KiB
LLVM
60 lines
1.2 KiB
LLVM
; bswap should be constant folded when it is passed a constant argument
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; RUN: llc < %s -march=x86 | FileCheck %s
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declare i16 @llvm.bswap.i16(i16)
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declare i32 @llvm.bswap.i32(i32)
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declare i64 @llvm.bswap.i64(i64)
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define i16 @W(i16 %A) {
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; CHECK: W:
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; CHECK: rolw $8, %ax
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%Z = call i16 @llvm.bswap.i16( i16 %A ) ; <i16> [#uses=1]
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ret i16 %Z
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}
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define i32 @X(i32 %A) {
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; CHECK: X:
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; CHECK: bswapl %eax
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%Z = call i32 @llvm.bswap.i32( i32 %A ) ; <i32> [#uses=1]
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ret i32 %Z
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}
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define i64 @Y(i64 %A) {
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; CHECK: Y:
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; CHECK: bswapl %eax
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; CHECK: bswapl %edx
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%Z = call i64 @llvm.bswap.i64( i64 %A ) ; <i64> [#uses=1]
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ret i64 %Z
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}
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; rdar://9164521
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define i32 @test1(i32 %a) nounwind readnone {
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entry:
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; CHECK: test1
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; CHECK: bswapl %eax
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; CHECK: shrl $16, %eax
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%and = lshr i32 %a, 8
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%shr3 = and i32 %and, 255
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%and2 = shl i32 %a, 8
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%shl = and i32 %and2, 65280
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%or = or i32 %shr3, %shl
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ret i32 %or
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}
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define i32 @test2(i32 %a) nounwind readnone {
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entry:
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; CHECK: test2
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; CHECK: bswapl %eax
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; CHECK: sarl $16, %eax
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%and = lshr i32 %a, 8
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%shr4 = and i32 %and, 255
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%and2 = shl i32 %a, 8
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%or = or i32 %shr4, %and2
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%sext = shl i32 %or, 16
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%conv3 = ashr exact i32 %sext, 16
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ret i32 %conv3
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}
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