mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-30 21:29:28 +00:00
isReg, etc., from isRegister, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57006 91177308-0d34-0410-b5e6-96231b3b80d8
1185 lines
43 KiB
C++
1185 lines
43 KiB
C++
//===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the X86 implementation of the TargetRegisterInfo class.
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// This file is responsible for the frame pointer elimination optimization
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// on X86.
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//
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "X86RegisterInfo.h"
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#include "X86InstrBuilder.h"
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#include "X86MachineFunctionInfo.h"
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#include "X86Subtarget.h"
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#include "X86TargetMachine.h"
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#include "llvm/Constants.h"
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#include "llvm/Function.h"
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#include "llvm/Type.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineLocation.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetAsmInfo.h"
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#include "llvm/Target/TargetFrameInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/Support/Compiler.h"
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using namespace llvm;
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X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
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const TargetInstrInfo &tii)
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: X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
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X86::ADJCALLSTACKDOWN64 :
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X86::ADJCALLSTACKDOWN32,
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tm.getSubtarget<X86Subtarget>().is64Bit() ?
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X86::ADJCALLSTACKUP64 :
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X86::ADJCALLSTACKUP32),
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TM(tm), TII(tii) {
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// Cache some information.
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const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
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Is64Bit = Subtarget->is64Bit();
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IsWin64 = Subtarget->isTargetWin64();
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StackAlign = TM.getFrameInfo()->getStackAlignment();
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if (Is64Bit) {
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SlotSize = 8;
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StackPtr = X86::RSP;
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FramePtr = X86::RBP;
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} else {
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SlotSize = 4;
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StackPtr = X86::ESP;
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FramePtr = X86::EBP;
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}
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}
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// getDwarfRegNum - This function maps LLVM register identifiers to the
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// Dwarf specific numbering, used in debug info and exception tables.
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int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
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const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
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unsigned Flavour = DWARFFlavour::X86_64;
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if (!Subtarget->is64Bit()) {
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if (Subtarget->isTargetDarwin()) {
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if (isEH)
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Flavour = DWARFFlavour::X86_32_DarwinEH;
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else
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Flavour = DWARFFlavour::X86_32_Generic;
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} else if (Subtarget->isTargetCygMing()) {
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// Unsupported by now, just quick fallback
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Flavour = DWARFFlavour::X86_32_Generic;
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} else {
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Flavour = DWARFFlavour::X86_32_Generic;
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}
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}
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return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
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}
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// getX86RegNum - This function maps LLVM register identifiers to their X86
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// specific numbering, which is used in various places encoding instructions.
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//
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unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
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switch(RegNo) {
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case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
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case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
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case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
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case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
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case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
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return N86::ESP;
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case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
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return N86::EBP;
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case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
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return N86::ESI;
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case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
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return N86::EDI;
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case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
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return N86::EAX;
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case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
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return N86::ECX;
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case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
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return N86::EDX;
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case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
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return N86::EBX;
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case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
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return N86::ESP;
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case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
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return N86::EBP;
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case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
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return N86::ESI;
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case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
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return N86::EDI;
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case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
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case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
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return RegNo-X86::ST0;
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case X86::XMM0: case X86::XMM8: case X86::MM0:
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return 0;
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case X86::XMM1: case X86::XMM9: case X86::MM1:
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return 1;
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case X86::XMM2: case X86::XMM10: case X86::MM2:
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return 2;
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case X86::XMM3: case X86::XMM11: case X86::MM3:
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return 3;
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case X86::XMM4: case X86::XMM12: case X86::MM4:
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return 4;
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case X86::XMM5: case X86::XMM13: case X86::MM5:
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return 5;
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case X86::XMM6: case X86::XMM14: case X86::MM6:
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return 6;
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case X86::XMM7: case X86::XMM15: case X86::MM7:
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return 7;
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default:
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assert(isVirtualRegister(RegNo) && "Unknown physical register!");
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assert(0 && "Register allocator hasn't allocated reg correctly yet!");
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return 0;
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}
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}
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const TargetRegisterClass *
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X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
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if (RC == &X86::CCRRegClass) {
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if (Is64Bit)
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return &X86::GR64RegClass;
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else
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return &X86::GR32RegClass;
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}
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return NULL;
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}
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const unsigned *
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X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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bool callsEHReturn = false;
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if (MF) {
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const MachineFrameInfo *MFI = MF->getFrameInfo();
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const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
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callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
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}
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static const unsigned CalleeSavedRegs32Bit[] = {
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X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
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};
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static const unsigned CalleeSavedRegs32EHRet[] = {
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X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
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};
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static const unsigned CalleeSavedRegs64Bit[] = {
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X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
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};
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static const unsigned CalleeSavedRegs64EHRet[] = {
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X86::RAX, X86::RDX, X86::RBX, X86::R12,
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X86::R13, X86::R14, X86::R15, X86::RBP, 0
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};
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static const unsigned CalleeSavedRegsWin64[] = {
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X86::RBX, X86::RBP, X86::RDI, X86::RSI,
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X86::R12, X86::R13, X86::R14, X86::R15,
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X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9,
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X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
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X86::XMM14, X86::XMM15, 0
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};
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if (Is64Bit) {
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if (IsWin64)
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return CalleeSavedRegsWin64;
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else
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return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
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} else {
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return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
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}
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}
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const TargetRegisterClass* const*
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X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
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bool callsEHReturn = false;
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if (MF) {
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const MachineFrameInfo *MFI = MF->getFrameInfo();
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const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
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callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
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}
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static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
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&X86::GR32RegClass, &X86::GR32RegClass,
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&X86::GR32RegClass, &X86::GR32RegClass, 0
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};
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static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
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&X86::GR32RegClass, &X86::GR32RegClass,
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&X86::GR32RegClass, &X86::GR32RegClass,
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&X86::GR32RegClass, &X86::GR32RegClass, 0
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};
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static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
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&X86::GR64RegClass, &X86::GR64RegClass,
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&X86::GR64RegClass, &X86::GR64RegClass,
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&X86::GR64RegClass, &X86::GR64RegClass, 0
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};
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static const TargetRegisterClass * const CalleeSavedRegClasses64EHRet[] = {
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&X86::GR64RegClass, &X86::GR64RegClass,
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&X86::GR64RegClass, &X86::GR64RegClass,
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&X86::GR64RegClass, &X86::GR64RegClass,
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&X86::GR64RegClass, &X86::GR64RegClass, 0
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};
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static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = {
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&X86::GR64RegClass, &X86::GR64RegClass,
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&X86::GR64RegClass, &X86::GR64RegClass,
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&X86::GR64RegClass, &X86::GR64RegClass,
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&X86::GR64RegClass, &X86::GR64RegClass,
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&X86::VR128RegClass, &X86::VR128RegClass,
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&X86::VR128RegClass, &X86::VR128RegClass,
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&X86::VR128RegClass, &X86::VR128RegClass,
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&X86::VR128RegClass, &X86::VR128RegClass,
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&X86::VR128RegClass, &X86::VR128RegClass, 0
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};
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if (Is64Bit) {
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if (IsWin64)
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return CalleeSavedRegClassesWin64;
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else
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return (callsEHReturn ?
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CalleeSavedRegClasses64EHRet : CalleeSavedRegClasses64Bit);
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} else {
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return (callsEHReturn ?
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CalleeSavedRegClasses32EHRet : CalleeSavedRegClasses32Bit);
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}
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}
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BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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Reserved.set(X86::RSP);
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Reserved.set(X86::ESP);
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Reserved.set(X86::SP);
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Reserved.set(X86::SPL);
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if (hasFP(MF)) {
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Reserved.set(X86::RBP);
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Reserved.set(X86::EBP);
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Reserved.set(X86::BP);
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Reserved.set(X86::BPL);
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}
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return Reserved;
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}
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//===----------------------------------------------------------------------===//
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// Stack Frame Processing methods
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//===----------------------------------------------------------------------===//
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static unsigned calculateMaxStackAlignment(const MachineFrameInfo *FFI) {
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unsigned MaxAlign = 0;
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for (int i = FFI->getObjectIndexBegin(),
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e = FFI->getObjectIndexEnd(); i != e; ++i) {
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if (FFI->isDeadObjectIndex(i))
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continue;
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unsigned Align = FFI->getObjectAlignment(i);
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MaxAlign = std::max(MaxAlign, Align);
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}
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return MaxAlign;
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}
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// hasFP - Return true if the specified function should have a dedicated frame
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// pointer register. This is true if the function has variable sized allocas or
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// if frame pointer elimination is disabled.
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//
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bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
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return (NoFramePointerElim ||
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needsStackRealignment(MF) ||
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MFI->hasVarSizedObjects() ||
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MFI->isFrameAddressTaken() ||
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MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
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(MMI && MMI->callsUnwindInit()));
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}
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bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
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const MachineFrameInfo *MFI = MF.getFrameInfo();;
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// FIXME: Currently we don't support stack realignment for functions with
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// variable-sized allocas
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return (RealignStack &&
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(MFI->getMaxAlignment() > StackAlign &&
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!MFI->hasVarSizedObjects()));
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}
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bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
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return !MF.getFrameInfo()->hasVarSizedObjects();
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}
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int
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X86RegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
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int Offset = MF.getFrameInfo()->getObjectOffset(FI) + SlotSize;
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uint64_t StackSize = MF.getFrameInfo()->getStackSize();
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if (needsStackRealignment(MF)) {
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if (FI < 0)
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// Skip the saved EBP
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Offset += SlotSize;
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else {
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unsigned Align = MF.getFrameInfo()->getObjectAlignment(FI);
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assert( (-(Offset + StackSize)) % Align == 0);
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return Offset + StackSize;
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}
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// FIXME: Support tail calls
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} else {
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if (!hasFP(MF))
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return Offset + StackSize;
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// Skip the saved EBP
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Offset += SlotSize;
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// Skip the RETADDR move area
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X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
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int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
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if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
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}
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return Offset;
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}
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void X86RegisterInfo::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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if (!hasReservedCallFrame(MF)) {
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// If the stack pointer can be changed after prologue, turn the
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// adjcallstackup instruction into a 'sub ESP, <amt>' and the
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// adjcallstackdown instruction into 'add ESP, <amt>'
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// TODO: consider using push / pop instead of sub + store / add
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MachineInstr *Old = I;
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uint64_t Amount = Old->getOperand(0).getImm();
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if (Amount != 0) {
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// We need to keep the stack aligned properly. To do this, we round the
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// amount of space needed for the outgoing arguments up to the next
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// alignment boundary.
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Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
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MachineInstr *New = 0;
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if (Old->getOpcode() == getCallFrameSetupOpcode()) {
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New = BuildMI(MF, TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri),
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StackPtr).addReg(StackPtr).addImm(Amount);
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} else {
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assert(Old->getOpcode() == getCallFrameDestroyOpcode());
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// factor out the amount the callee already popped.
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uint64_t CalleeAmt = Old->getOperand(1).getImm();
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Amount -= CalleeAmt;
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if (Amount) {
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unsigned Opc = (Amount < 128) ?
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(Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
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(Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
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New = BuildMI(MF, TII.get(Opc), StackPtr)
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.addReg(StackPtr).addImm(Amount);
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}
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}
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// Replace the pseudo instruction with a new instruction...
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if (New) MBB.insert(I, New);
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}
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} else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
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// If we are performing frame pointer elimination and if the callee pops
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// something off the stack pointer, add it back. We do this until we have
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// more advanced stack pointer tracking ability.
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if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
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unsigned Opc = (CalleeAmt < 128) ?
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(Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
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(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
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MachineInstr *New =
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BuildMI(MF, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt);
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MBB.insert(I, New);
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}
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}
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MBB.erase(I);
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}
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void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, RegScavenger *RS) const{
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assert(SPAdj == 0 && "Unexpected");
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unsigned i = 0;
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MachineInstr &MI = *II;
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MachineFunction &MF = *MI.getParent()->getParent();
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while (!MI.getOperand(i).isFI()) {
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++i;
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assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
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}
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int FrameIndex = MI.getOperand(i).getIndex();
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unsigned BasePtr;
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if (needsStackRealignment(MF))
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BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
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else
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BasePtr = (hasFP(MF) ? FramePtr : StackPtr);
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// This must be part of a four operand memory reference. Replace the
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// FrameIndex with base register with EBP. Add an offset to the offset.
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MI.getOperand(i).ChangeToRegister(BasePtr, false);
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|
|
// Now add the frame object offset to the offset from EBP. Offset is a
|
|
// 32-bit integer.
|
|
int Offset = getFrameIndexOffset(MF, FrameIndex) +
|
|
(int)(MI.getOperand(i+3).getImm());
|
|
|
|
MI.getOperand(i+3).ChangeToImmediate(Offset);
|
|
}
|
|
|
|
void
|
|
X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
|
|
RegScavenger *RS) const {
|
|
MachineFrameInfo *FFI = MF.getFrameInfo();
|
|
|
|
// Calculate and set max stack object alignment early, so we can decide
|
|
// whether we will need stack realignment (and thus FP).
|
|
unsigned MaxAlign = std::max(FFI->getMaxAlignment(),
|
|
calculateMaxStackAlignment(FFI));
|
|
|
|
FFI->setMaxAlignment(MaxAlign);
|
|
}
|
|
|
|
void
|
|
X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
|
|
X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
|
|
int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
|
|
if (TailCallReturnAddrDelta < 0) {
|
|
// create RETURNADDR area
|
|
// arg
|
|
// arg
|
|
// RETADDR
|
|
// { ...
|
|
// RETADDR area
|
|
// ...
|
|
// }
|
|
// [EBP]
|
|
MF.getFrameInfo()->
|
|
CreateFixedObject(-TailCallReturnAddrDelta,
|
|
(-1*SlotSize)+TailCallReturnAddrDelta);
|
|
}
|
|
if (hasFP(MF)) {
|
|
assert((TailCallReturnAddrDelta <= 0) &&
|
|
"The Delta should always be zero or negative");
|
|
// Create a frame entry for the EBP register that must be saved.
|
|
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,
|
|
(int)SlotSize * -2+
|
|
TailCallReturnAddrDelta);
|
|
assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
|
|
"Slot for EBP register must be last in order to be found!");
|
|
}
|
|
}
|
|
|
|
/// emitSPUpdate - Emit a series of instructions to increment / decrement the
|
|
/// stack pointer by a constant value.
|
|
static
|
|
void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
|
|
unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
|
|
const TargetInstrInfo &TII) {
|
|
bool isSub = NumBytes < 0;
|
|
uint64_t Offset = isSub ? -NumBytes : NumBytes;
|
|
unsigned Opc = isSub
|
|
? ((Offset < 128) ?
|
|
(Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
|
|
(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
|
|
: ((Offset < 128) ?
|
|
(Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
|
|
(Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
|
|
uint64_t Chunk = (1LL << 31) - 1;
|
|
|
|
while (Offset) {
|
|
uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
|
|
BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(ThisVal);
|
|
Offset -= ThisVal;
|
|
}
|
|
}
|
|
|
|
// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
|
|
static
|
|
void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
|
|
unsigned StackPtr, uint64_t *NumBytes = NULL) {
|
|
if (MBBI == MBB.begin()) return;
|
|
|
|
MachineBasicBlock::iterator PI = prior(MBBI);
|
|
unsigned Opc = PI->getOpcode();
|
|
if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
|
|
Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
|
|
PI->getOperand(0).getReg() == StackPtr) {
|
|
if (NumBytes)
|
|
*NumBytes += PI->getOperand(2).getImm();
|
|
MBB.erase(PI);
|
|
} else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
|
|
Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
|
|
PI->getOperand(0).getReg() == StackPtr) {
|
|
if (NumBytes)
|
|
*NumBytes -= PI->getOperand(2).getImm();
|
|
MBB.erase(PI);
|
|
}
|
|
}
|
|
|
|
// mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
|
|
static
|
|
void mergeSPUpdatesDown(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator &MBBI,
|
|
unsigned StackPtr, uint64_t *NumBytes = NULL) {
|
|
return;
|
|
|
|
if (MBBI == MBB.end()) return;
|
|
|
|
MachineBasicBlock::iterator NI = next(MBBI);
|
|
if (NI == MBB.end()) return;
|
|
|
|
unsigned Opc = NI->getOpcode();
|
|
if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
|
|
Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
|
|
NI->getOperand(0).getReg() == StackPtr) {
|
|
if (NumBytes)
|
|
*NumBytes -= NI->getOperand(2).getImm();
|
|
MBB.erase(NI);
|
|
MBBI = NI;
|
|
} else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
|
|
Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
|
|
NI->getOperand(0).getReg() == StackPtr) {
|
|
if (NumBytes)
|
|
*NumBytes += NI->getOperand(2).getImm();
|
|
MBB.erase(NI);
|
|
MBBI = NI;
|
|
}
|
|
}
|
|
|
|
/// mergeSPUpdates - Checks the instruction before/after the passed
|
|
/// instruction. If it is an ADD/SUB instruction it is deleted
|
|
/// argument and the stack adjustment is returned as a positive value for ADD
|
|
/// and a negative for SUB.
|
|
static int mergeSPUpdates(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator &MBBI,
|
|
unsigned StackPtr,
|
|
bool doMergeWithPrevious) {
|
|
|
|
if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
|
|
(!doMergeWithPrevious && MBBI == MBB.end()))
|
|
return 0;
|
|
|
|
int Offset = 0;
|
|
|
|
MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
|
|
MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI);
|
|
unsigned Opc = PI->getOpcode();
|
|
if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
|
|
Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
|
|
PI->getOperand(0).getReg() == StackPtr){
|
|
Offset += PI->getOperand(2).getImm();
|
|
MBB.erase(PI);
|
|
if (!doMergeWithPrevious) MBBI = NI;
|
|
} else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
|
|
Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
|
|
PI->getOperand(0).getReg() == StackPtr) {
|
|
Offset -= PI->getOperand(2).getImm();
|
|
MBB.erase(PI);
|
|
if (!doMergeWithPrevious) MBBI = NI;
|
|
}
|
|
|
|
return Offset;
|
|
}
|
|
|
|
void X86RegisterInfo::emitFrameMoves(MachineFunction &MF,
|
|
unsigned FrameLabelId,
|
|
unsigned ReadyLabelId) const {
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
|
|
if (!MMI)
|
|
return;
|
|
|
|
uint64_t StackSize = MFI->getStackSize();
|
|
std::vector<MachineMove> &Moves = MMI->getFrameMoves();
|
|
const TargetData *TD = MF.getTarget().getTargetData();
|
|
|
|
// Calculate amount of bytes used for return address storing
|
|
int stackGrowth =
|
|
(MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
|
|
TargetFrameInfo::StackGrowsUp ?
|
|
TD->getPointerSize() : -TD->getPointerSize());
|
|
|
|
if (StackSize) {
|
|
// Show update of SP.
|
|
if (hasFP(MF)) {
|
|
// Adjust SP
|
|
MachineLocation SPDst(MachineLocation::VirtualFP);
|
|
MachineLocation SPSrc(MachineLocation::VirtualFP, 2*stackGrowth);
|
|
Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
|
|
} else {
|
|
MachineLocation SPDst(MachineLocation::VirtualFP);
|
|
MachineLocation SPSrc(MachineLocation::VirtualFP,
|
|
-StackSize+stackGrowth);
|
|
Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
|
|
}
|
|
} else {
|
|
//FIXME: Verify & implement for FP
|
|
MachineLocation SPDst(StackPtr);
|
|
MachineLocation SPSrc(StackPtr, stackGrowth);
|
|
Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
|
|
}
|
|
|
|
// Add callee saved registers to move list.
|
|
const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
|
|
|
|
// FIXME: This is dirty hack. The code itself is pretty mess right now.
|
|
// It should be rewritten from scratch and generalized sometimes.
|
|
|
|
// Determine maximum offset (minumum due to stack growth)
|
|
int64_t MaxOffset = 0;
|
|
for (unsigned I = 0, E = CSI.size(); I!=E; ++I)
|
|
MaxOffset = std::min(MaxOffset,
|
|
MFI->getObjectOffset(CSI[I].getFrameIdx()));
|
|
|
|
// Calculate offsets
|
|
int64_t saveAreaOffset = (hasFP(MF) ? 3 : 2)*stackGrowth;
|
|
for (unsigned I = 0, E = CSI.size(); I!=E; ++I) {
|
|
int64_t Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
|
|
unsigned Reg = CSI[I].getReg();
|
|
Offset = (MaxOffset-Offset+saveAreaOffset);
|
|
MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
|
|
MachineLocation CSSrc(Reg);
|
|
Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
|
|
}
|
|
|
|
if (hasFP(MF)) {
|
|
// Save FP
|
|
MachineLocation FPDst(MachineLocation::VirtualFP, 2*stackGrowth);
|
|
MachineLocation FPSrc(FramePtr);
|
|
Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
|
|
}
|
|
|
|
MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr);
|
|
MachineLocation FPSrc(MachineLocation::VirtualFP);
|
|
Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
|
|
}
|
|
|
|
|
|
void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
|
|
MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
const Function* Fn = MF.getFunction();
|
|
const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
|
|
MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
|
|
X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
|
|
MachineBasicBlock::iterator MBBI = MBB.begin();
|
|
bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
|
|
!Fn->doesNotThrow() ||
|
|
UnwindTablesMandatory;
|
|
// Prepare for frame info.
|
|
unsigned FrameLabelId = 0;
|
|
|
|
// Get the number of bytes to allocate from the FrameInfo.
|
|
uint64_t StackSize = MFI->getStackSize();
|
|
// Get desired stack alignment
|
|
uint64_t MaxAlign = MFI->getMaxAlignment();
|
|
|
|
// Add RETADDR move area to callee saved frame size.
|
|
int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
|
|
if (TailCallReturnAddrDelta < 0)
|
|
X86FI->setCalleeSavedFrameSize(
|
|
X86FI->getCalleeSavedFrameSize() +(-TailCallReturnAddrDelta));
|
|
|
|
// Insert stack pointer adjustment for later moving of return addr. Only
|
|
// applies to tail call optimized functions where the callee argument stack
|
|
// size is bigger than the callers.
|
|
if (TailCallReturnAddrDelta < 0) {
|
|
BuildMI(MBB, MBBI, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
|
|
StackPtr).addReg(StackPtr).addImm(-TailCallReturnAddrDelta);
|
|
}
|
|
|
|
uint64_t NumBytes = 0;
|
|
if (hasFP(MF)) {
|
|
// Calculate required stack adjustment
|
|
uint64_t FrameSize = StackSize - SlotSize;
|
|
if (needsStackRealignment(MF))
|
|
FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
|
|
|
|
NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
|
|
|
|
// Get the offset of the stack slot for the EBP register... which is
|
|
// guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
|
|
// Update the frame offset adjustment.
|
|
MFI->setOffsetAdjustment(-NumBytes);
|
|
|
|
// Save EBP into the appropriate stack slot...
|
|
BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
|
|
.addReg(FramePtr);
|
|
|
|
if (needsFrameMoves) {
|
|
// Mark effective beginning of when frame pointer becomes valid.
|
|
FrameLabelId = MMI->NextLabelID();
|
|
BuildMI(MBB, MBBI, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
|
|
}
|
|
|
|
// Update EBP with the new base value...
|
|
BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
|
|
.addReg(StackPtr);
|
|
|
|
// Realign stack
|
|
if (needsStackRealignment(MF))
|
|
BuildMI(MBB, MBBI,
|
|
TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
|
|
StackPtr).addReg(StackPtr).addImm(-MaxAlign);
|
|
} else
|
|
NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
|
|
|
|
unsigned ReadyLabelId = 0;
|
|
if (needsFrameMoves) {
|
|
// Mark effective beginning of when frame pointer is ready.
|
|
ReadyLabelId = MMI->NextLabelID();
|
|
BuildMI(MBB, MBBI, TII.get(X86::DBG_LABEL)).addImm(ReadyLabelId);
|
|
}
|
|
|
|
// Skip the callee-saved push instructions.
|
|
while (MBBI != MBB.end() &&
|
|
(MBBI->getOpcode() == X86::PUSH32r ||
|
|
MBBI->getOpcode() == X86::PUSH64r))
|
|
++MBBI;
|
|
|
|
if (NumBytes) { // adjust stack pointer: ESP -= numbytes
|
|
if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
|
|
// Check, whether EAX is livein for this function
|
|
bool isEAXAlive = false;
|
|
for (MachineRegisterInfo::livein_iterator
|
|
II = MF.getRegInfo().livein_begin(),
|
|
EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
|
|
unsigned Reg = II->first;
|
|
isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
|
|
Reg == X86::AH || Reg == X86::AL);
|
|
}
|
|
|
|
// Function prologue calls _alloca to probe the stack when allocating
|
|
// more than 4k bytes in one go. Touching the stack at 4K increments is
|
|
// necessary to ensure that the guard pages used by the OS virtual memory
|
|
// manager are allocated in correct sequence.
|
|
if (!isEAXAlive) {
|
|
BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes);
|
|
BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
|
|
.addExternalSymbol("_alloca");
|
|
} else {
|
|
// Save EAX
|
|
BuildMI(MBB, MBBI, TII.get(X86::PUSH32r), X86::EAX);
|
|
// Allocate NumBytes-4 bytes on stack. We'll also use 4 already
|
|
// allocated bytes for EAX.
|
|
BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes-4);
|
|
BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
|
|
.addExternalSymbol("_alloca");
|
|
// Restore EAX
|
|
MachineInstr *MI = addRegOffset(BuildMI(MF, TII.get(X86::MOV32rm),X86::EAX),
|
|
StackPtr, false, NumBytes-4);
|
|
MBB.insert(MBBI, MI);
|
|
}
|
|
} else {
|
|
// If there is an SUB32ri of ESP immediately before this instruction,
|
|
// merge the two. This can be the case when tail call elimination is
|
|
// enabled and the callee has more arguments then the caller.
|
|
NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
|
|
// If there is an ADD32ri or SUB32ri of ESP immediately after this
|
|
// instruction, merge the two instructions.
|
|
mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
|
|
|
|
if (NumBytes)
|
|
emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
|
|
}
|
|
}
|
|
|
|
if (needsFrameMoves)
|
|
emitFrameMoves(MF, FrameLabelId, ReadyLabelId);
|
|
}
|
|
|
|
void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
|
|
MachineBasicBlock &MBB) const {
|
|
const MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
|
|
MachineBasicBlock::iterator MBBI = prior(MBB.end());
|
|
unsigned RetOpcode = MBBI->getOpcode();
|
|
|
|
switch (RetOpcode) {
|
|
case X86::RET:
|
|
case X86::RETI:
|
|
case X86::TCRETURNdi:
|
|
case X86::TCRETURNri:
|
|
case X86::TCRETURNri64:
|
|
case X86::TCRETURNdi64:
|
|
case X86::EH_RETURN:
|
|
case X86::EH_RETURN64:
|
|
case X86::TAILJMPd:
|
|
case X86::TAILJMPr:
|
|
case X86::TAILJMPm: break; // These are ok
|
|
default:
|
|
assert(0 && "Can only insert epilog into returning blocks");
|
|
}
|
|
|
|
// Get the number of bytes to allocate from the FrameInfo
|
|
uint64_t StackSize = MFI->getStackSize();
|
|
uint64_t MaxAlign = MFI->getMaxAlignment();
|
|
unsigned CSSize = X86FI->getCalleeSavedFrameSize();
|
|
uint64_t NumBytes = 0;
|
|
|
|
if (hasFP(MF)) {
|
|
// Calculate required stack adjustment
|
|
uint64_t FrameSize = StackSize - SlotSize;
|
|
if (needsStackRealignment(MF))
|
|
FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
|
|
|
|
NumBytes = FrameSize - CSSize;
|
|
|
|
// pop EBP.
|
|
BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
|
|
} else
|
|
NumBytes = StackSize - CSSize;
|
|
|
|
// Skip the callee-saved pop instructions.
|
|
MachineBasicBlock::iterator LastCSPop = MBBI;
|
|
while (MBBI != MBB.begin()) {
|
|
MachineBasicBlock::iterator PI = prior(MBBI);
|
|
unsigned Opc = PI->getOpcode();
|
|
if (Opc != X86::POP32r && Opc != X86::POP64r &&
|
|
!PI->getDesc().isTerminator())
|
|
break;
|
|
--MBBI;
|
|
}
|
|
|
|
// If there is an ADD32ri or SUB32ri of ESP immediately before this
|
|
// instruction, merge the two instructions.
|
|
if (NumBytes || MFI->hasVarSizedObjects())
|
|
mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
|
|
|
|
// If dynamic alloca is used, then reset esp to point to the last callee-saved
|
|
// slot before popping them off! Same applies for the case, when stack was
|
|
// realigned
|
|
if (needsStackRealignment(MF)) {
|
|
// We cannot use LEA here, because stack pointer was realigned. We need to
|
|
// deallocate local frame back
|
|
if (CSSize) {
|
|
emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
|
|
MBBI = prior(LastCSPop);
|
|
}
|
|
|
|
BuildMI(MBB, MBBI,
|
|
TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
|
|
StackPtr).addReg(FramePtr);
|
|
} else if (MFI->hasVarSizedObjects()) {
|
|
if (CSSize) {
|
|
unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
|
|
MachineInstr *MI = addRegOffset(BuildMI(MF, TII.get(Opc), StackPtr),
|
|
FramePtr, false, -CSSize);
|
|
MBB.insert(MBBI, MI);
|
|
} else
|
|
BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
|
|
StackPtr).addReg(FramePtr);
|
|
|
|
} else {
|
|
// adjust stack pointer back: ESP += numbytes
|
|
if (NumBytes)
|
|
emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
|
|
}
|
|
|
|
// We're returning from function via eh_return.
|
|
if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
|
|
MBBI = prior(MBB.end());
|
|
MachineOperand &DestAddr = MBBI->getOperand(0);
|
|
assert(DestAddr.isReg() && "Offset should be in register!");
|
|
BuildMI(MBB, MBBI,
|
|
TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
|
|
StackPtr).addReg(DestAddr.getReg());
|
|
// Tail call return: adjust the stack pointer and jump to callee
|
|
} else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
|
|
RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
|
|
MBBI = prior(MBB.end());
|
|
MachineOperand &JumpTarget = MBBI->getOperand(0);
|
|
MachineOperand &StackAdjust = MBBI->getOperand(1);
|
|
assert(StackAdjust.isImm() && "Expecting immediate value.");
|
|
|
|
// Adjust stack pointer.
|
|
int StackAdj = StackAdjust.getImm();
|
|
int MaxTCDelta = X86FI->getTCReturnAddrDelta();
|
|
int Offset = 0;
|
|
assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
|
|
// Incoporate the retaddr area.
|
|
Offset = StackAdj-MaxTCDelta;
|
|
assert(Offset >= 0 && "Offset should never be negative");
|
|
if (Offset) {
|
|
// Check for possible merge with preceeding ADD instruction.
|
|
Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
|
|
emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
|
|
}
|
|
// Jump to label or value in register.
|
|
if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
|
|
BuildMI(MBB, MBBI, TII.get(X86::TAILJMPd)).
|
|
addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
|
|
else if (RetOpcode== X86::TCRETURNri64) {
|
|
BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
|
|
} else
|
|
BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr), JumpTarget.getReg());
|
|
// Delete the pseudo instruction TCRETURN.
|
|
MBB.erase(MBBI);
|
|
} else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
|
|
(X86FI->getTCReturnAddrDelta() < 0)) {
|
|
// Add the return addr area delta back since we are not tail calling.
|
|
int delta = -1*X86FI->getTCReturnAddrDelta();
|
|
MBBI = prior(MBB.end());
|
|
// Check for possible merge with preceeding ADD instruction.
|
|
delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
|
|
emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
|
|
}
|
|
}
|
|
|
|
unsigned X86RegisterInfo::getRARegister() const {
|
|
if (Is64Bit)
|
|
return X86::RIP; // Should have dwarf #16
|
|
else
|
|
return X86::EIP; // Should have dwarf #8
|
|
}
|
|
|
|
unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
|
|
return hasFP(MF) ? FramePtr : StackPtr;
|
|
}
|
|
|
|
void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
|
|
const {
|
|
// Calculate amount of bytes used for return address storing
|
|
int stackGrowth = (Is64Bit ? -8 : -4);
|
|
|
|
// Initial state of the frame pointer is esp+4.
|
|
MachineLocation Dst(MachineLocation::VirtualFP);
|
|
MachineLocation Src(StackPtr, stackGrowth);
|
|
Moves.push_back(MachineMove(0, Dst, Src));
|
|
|
|
// Add return address to move list
|
|
MachineLocation CSDst(StackPtr, stackGrowth);
|
|
MachineLocation CSSrc(getRARegister());
|
|
Moves.push_back(MachineMove(0, CSDst, CSSrc));
|
|
}
|
|
|
|
unsigned X86RegisterInfo::getEHExceptionRegister() const {
|
|
assert(0 && "What is the exception register");
|
|
return 0;
|
|
}
|
|
|
|
unsigned X86RegisterInfo::getEHHandlerRegister() const {
|
|
assert(0 && "What is the exception handler register");
|
|
return 0;
|
|
}
|
|
|
|
namespace llvm {
|
|
unsigned getX86SubSuperRegister(unsigned Reg, MVT VT, bool High) {
|
|
switch (VT.getSimpleVT()) {
|
|
default: return Reg;
|
|
case MVT::i8:
|
|
if (High) {
|
|
switch (Reg) {
|
|
default: return 0;
|
|
case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
|
|
return X86::AH;
|
|
case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
|
|
return X86::DH;
|
|
case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
|
|
return X86::CH;
|
|
case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
|
|
return X86::BH;
|
|
}
|
|
} else {
|
|
switch (Reg) {
|
|
default: return 0;
|
|
case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
|
|
return X86::AL;
|
|
case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
|
|
return X86::DL;
|
|
case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
|
|
return X86::CL;
|
|
case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
|
|
return X86::BL;
|
|
case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
|
|
return X86::SIL;
|
|
case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
|
|
return X86::DIL;
|
|
case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
|
|
return X86::BPL;
|
|
case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
|
|
return X86::SPL;
|
|
case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
|
|
return X86::R8B;
|
|
case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
|
|
return X86::R9B;
|
|
case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
|
|
return X86::R10B;
|
|
case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
|
|
return X86::R11B;
|
|
case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
|
|
return X86::R12B;
|
|
case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
|
|
return X86::R13B;
|
|
case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
|
|
return X86::R14B;
|
|
case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
|
|
return X86::R15B;
|
|
}
|
|
}
|
|
case MVT::i16:
|
|
switch (Reg) {
|
|
default: return Reg;
|
|
case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
|
|
return X86::AX;
|
|
case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
|
|
return X86::DX;
|
|
case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
|
|
return X86::CX;
|
|
case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
|
|
return X86::BX;
|
|
case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
|
|
return X86::SI;
|
|
case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
|
|
return X86::DI;
|
|
case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
|
|
return X86::BP;
|
|
case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
|
|
return X86::SP;
|
|
case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
|
|
return X86::R8W;
|
|
case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
|
|
return X86::R9W;
|
|
case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
|
|
return X86::R10W;
|
|
case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
|
|
return X86::R11W;
|
|
case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
|
|
return X86::R12W;
|
|
case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
|
|
return X86::R13W;
|
|
case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
|
|
return X86::R14W;
|
|
case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
|
|
return X86::R15W;
|
|
}
|
|
case MVT::i32:
|
|
switch (Reg) {
|
|
default: return Reg;
|
|
case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
|
|
return X86::EAX;
|
|
case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
|
|
return X86::EDX;
|
|
case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
|
|
return X86::ECX;
|
|
case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
|
|
return X86::EBX;
|
|
case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
|
|
return X86::ESI;
|
|
case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
|
|
return X86::EDI;
|
|
case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
|
|
return X86::EBP;
|
|
case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
|
|
return X86::ESP;
|
|
case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
|
|
return X86::R8D;
|
|
case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
|
|
return X86::R9D;
|
|
case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
|
|
return X86::R10D;
|
|
case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
|
|
return X86::R11D;
|
|
case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
|
|
return X86::R12D;
|
|
case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
|
|
return X86::R13D;
|
|
case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
|
|
return X86::R14D;
|
|
case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
|
|
return X86::R15D;
|
|
}
|
|
case MVT::i64:
|
|
switch (Reg) {
|
|
default: return Reg;
|
|
case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
|
|
return X86::RAX;
|
|
case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
|
|
return X86::RDX;
|
|
case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
|
|
return X86::RCX;
|
|
case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
|
|
return X86::RBX;
|
|
case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
|
|
return X86::RSI;
|
|
case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
|
|
return X86::RDI;
|
|
case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
|
|
return X86::RBP;
|
|
case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
|
|
return X86::RSP;
|
|
case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
|
|
return X86::R8;
|
|
case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
|
|
return X86::R9;
|
|
case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
|
|
return X86::R10;
|
|
case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
|
|
return X86::R11;
|
|
case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
|
|
return X86::R12;
|
|
case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
|
|
return X86::R13;
|
|
case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
|
|
return X86::R14;
|
|
case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
|
|
return X86::R15;
|
|
}
|
|
}
|
|
|
|
return Reg;
|
|
}
|
|
}
|
|
|
|
#include "X86GenRegisterInfo.inc"
|
|
|
|
namespace {
|
|
struct VISIBILITY_HIDDEN MSAC : public MachineFunctionPass {
|
|
static char ID;
|
|
MSAC() : MachineFunctionPass(&ID) {}
|
|
|
|
virtual bool runOnMachineFunction(MachineFunction &MF) {
|
|
MachineFrameInfo *FFI = MF.getFrameInfo();
|
|
MachineRegisterInfo &RI = MF.getRegInfo();
|
|
|
|
// Calculate max stack alignment of all already allocated stack objects.
|
|
unsigned MaxAlign = calculateMaxStackAlignment(FFI);
|
|
|
|
// Be over-conservative: scan over all vreg defs and find, whether vector
|
|
// registers are used. If yes - there is probability, that vector register
|
|
// will be spilled and thus stack needs to be aligned properly.
|
|
for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister;
|
|
RegNum < RI.getLastVirtReg(); ++RegNum)
|
|
MaxAlign = std::max(MaxAlign, RI.getRegClass(RegNum)->getAlignment());
|
|
|
|
FFI->setMaxAlignment(MaxAlign);
|
|
|
|
return false;
|
|
}
|
|
|
|
virtual const char *getPassName() const {
|
|
return "X86 Maximal Stack Alignment Calculator";
|
|
}
|
|
};
|
|
|
|
char MSAC::ID = 0;
|
|
}
|
|
|
|
FunctionPass*
|
|
llvm::createX86MaxStackAlignmentCalculatorPass() { return new MSAC(); }
|