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and better control the abstraction. Rename the type to MVT. To update out-of-tree patches, the main thing to do is to rename MVT::ValueType to MVT, and rewrite expressions like MVT::getSizeInBits(VT) in the form VT.getSizeInBits(). Use VT.getSimpleVT() to extract a MVT::SimpleValueType for use in switch statements (you will get an assert failure if VT is an extended value type - these shouldn't exist after type legalization). This results in a small speedup of codegen and no new testsuite failures (x86-64 linux). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52044 91177308-0d34-0410-b5e6-96231b3b80d8
158 lines
5.0 KiB
C++
158 lines
5.0 KiB
C++
//===- X86RegisterInfo.h - X86 Register Information Impl --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the X86 implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef X86REGISTERINFO_H
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#define X86REGISTERINFO_H
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "X86GenRegisterInfo.h.inc"
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namespace llvm {
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class Type;
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class TargetInstrInfo;
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class X86TargetMachine;
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/// N86 namespace - Native X86 register numbers
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///
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namespace N86 {
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enum {
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EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
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};
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}
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namespace X86 {
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/// SubregIndex - The index of various sized subregister classes. Note that
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/// these indices must be kept in sync with the class indices in the
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/// X86RegisterInfo.td file.
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enum SubregIndex {
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SUBREG_8BIT = 1, SUBREG_16BIT = 2, SUBREG_32BIT = 3
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};
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}
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/// DWARFFlavour - Flavour of dwarf regnumbers
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///
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namespace DWARFFlavour {
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enum {
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X86_64 = 0, X86_32_DarwinEH = 1, X86_32_Generic = 2
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};
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}
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class X86RegisterInfo : public X86GenRegisterInfo {
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public:
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X86TargetMachine &TM;
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const TargetInstrInfo &TII;
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private:
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/// Is64Bit - Is the target 64-bits.
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///
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bool Is64Bit;
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/// IsWin64 - Is the target on of win64 flavours
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///
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bool IsWin64;
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/// SlotSize - Stack slot size in bytes.
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///
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unsigned SlotSize;
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/// StackAlign - Default stack alignment.
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///
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unsigned StackAlign;
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/// StackPtr - X86 physical register used as stack ptr.
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///
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unsigned StackPtr;
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/// FramePtr - X86 physical register used as frame ptr.
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///
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unsigned FramePtr;
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public:
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X86RegisterInfo(X86TargetMachine &tm, const TargetInstrInfo &tii);
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/// getX86RegNum - Returns the native X86 register number for the given LLVM
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/// register identifier.
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static unsigned getX86RegNum(unsigned RegNo);
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unsigned getStackAlignment() const { return StackAlign; }
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/// getDwarfRegNum - allows modification of X86GenRegisterInfo::getDwarfRegNum
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/// (created by TableGen) for target dependencies.
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int getDwarfRegNum(unsigned RegNum, bool isEH) const;
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/// Code Generation virtual methods...
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///
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const TargetRegisterClass *
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getCrossCopyRegClass(const TargetRegisterClass *RC) const;
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/// getCalleeSavedRegs - Return a null-terminated list of all of the
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/// callee-save registers on this target.
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const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
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/// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
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/// register classes to spill each callee-saved register with. The order and
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/// length of this list match the getCalleeSavedRegs() list.
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const TargetRegisterClass* const*
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getCalleeSavedRegClasses(const MachineFunction *MF = 0) const;
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/// getReservedRegs - Returns a bitset indexed by physical register number
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/// indicating if a register is a special register that has particular uses and
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/// should be considered unavailable at all times, e.g. SP, RA. This is used by
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/// register scavenger to determine what registers are free.
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BitVector getReservedRegs(const MachineFunction &MF) const;
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bool hasFP(const MachineFunction &MF) const;
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bool needsStackRealignment(const MachineFunction &MF) const;
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bool hasReservedCallFrame(MachineFunction &MF) const;
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void eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const;
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void eliminateFrameIndex(MachineBasicBlock::iterator MI,
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int SPAdj, RegScavenger *RS = NULL) const;
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void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
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void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
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RegScavenger *RS = NULL) const;
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void emitPrologue(MachineFunction &MF) const;
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void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
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void emitFrameMoves(MachineFunction &MF,
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unsigned FrameLabelId, unsigned ReadyLabelId) const;
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// Debug information queries.
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unsigned getRARegister() const;
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unsigned getFrameRegister(MachineFunction &MF) const;
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int getFrameIndexOffset(MachineFunction &MF, int FI) const;
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void getInitialFrameState(std::vector<MachineMove> &Moves) const;
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// Exception handling queries.
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unsigned getEHExceptionRegister() const;
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unsigned getEHHandlerRegister() const;
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};
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// getX86SubSuperRegister - X86 utility function. It returns the sub or super
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// register of a specific X86 register.
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// e.g. getX86SubSuperRegister(X86::EAX, MVT::i16) return X86:AX
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unsigned getX86SubSuperRegister(unsigned, MVT, bool High=false);
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} // End llvm namespace
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#endif
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