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44b486ed78
Before this change, the SystemZ backend would use BRCL for all branches
and only consider shortening them to BRC when generating an object file.
E.g. a branch on equal would use the JGE alias of BRCL in assembly output,
but might be shortened to the JE alias of BRC in ELF output. This was
a useful first step, but it had two problems:
(1) The z assembler isn't traditionally supposed to perform branch shortening
or branch relaxation. We followed this rule by not relaxing branches
in assembler input, but that meant that generating assembly code and
then assembling it would not produce the same result as going directly
to object code; the former would give long branches everywhere, whereas
the latter would use short branches where possible.
(2) Other useful branches, like COMPARE AND BRANCH, do not have long forms.
We would need to do something else before supporting them.
(Although COMPARE AND BRANCH does not change the condition codes,
the plan is to model COMPARE AND BRANCH as a CC-clobbering instruction
during codegen, so that we can safely lower it to a separate compare
and long branch where necessary. This is not a valid transformation
for the assembler proper to make.)
This patch therefore moves branch relaxation to a pre-emit pass.
For now, calls are still shortened from BRASL to BRAS by the assembler,
although this too is not really the traditional behaviour.
The first test takes about 1.5s to run, and there are likely to be
more tests in this vein once further branch types are added. The feeling
on IRC was that 1.5s is a bit much for a single test, so I've restricted
it to SystemZ hosts for now.
The patch exposes (and fixes) some typos in the main CodeGen/SystemZ tests.
A later patch will remove the {{g}}s from that directory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182274 91177308-0d34-0410-b5e6-96231b3b80d8
112 lines
3.9 KiB
C++
112 lines
3.9 KiB
C++
//===-- SystemZMCInstLower.cpp - Lower MachineInstr to MCInst -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "SystemZMCInstLower.h"
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#include "SystemZAsmPrinter.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/Target/Mangler.h"
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using namespace llvm;
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// If Opcode is an interprocedural reference that can be shortened,
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// return the short form, otherwise return 0.
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static unsigned getShortenedInstr(unsigned Opcode) {
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switch (Opcode) {
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case SystemZ::BRASL: return SystemZ::BRAS;
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}
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return Opcode;
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}
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// Return the VK_* enumeration for MachineOperand target flags Flags.
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static MCSymbolRefExpr::VariantKind getVariantKind(unsigned Flags) {
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switch (Flags & SystemZII::MO_SYMBOL_MODIFIER) {
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case 0:
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return MCSymbolRefExpr::VK_None;
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case SystemZII::MO_GOT:
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return MCSymbolRefExpr::VK_GOT;
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}
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llvm_unreachable("Unrecognised MO_ACCESS_MODEL");
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}
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SystemZMCInstLower::SystemZMCInstLower(Mangler *mang, MCContext &ctx,
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SystemZAsmPrinter &asmprinter)
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: Mang(mang), Ctx(ctx), AsmPrinter(asmprinter) {}
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MCOperand SystemZMCInstLower::lowerSymbolOperand(const MachineOperand &MO,
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const MCSymbol *Symbol,
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int64_t Offset) const {
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MCSymbolRefExpr::VariantKind Kind = getVariantKind(MO.getTargetFlags());
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const MCExpr *Expr = MCSymbolRefExpr::Create(Symbol, Kind, Ctx);
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if (Offset) {
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const MCExpr *OffsetExpr = MCConstantExpr::Create(Offset, Ctx);
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Expr = MCBinaryExpr::CreateAdd(Expr, OffsetExpr, Ctx);
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}
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return MCOperand::CreateExpr(Expr);
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}
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MCOperand SystemZMCInstLower::lowerOperand(const MachineOperand &MO) const {
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switch (MO.getType()) {
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default:
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llvm_unreachable("unknown operand type");
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case MachineOperand::MO_Register:
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// Ignore all implicit register operands.
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if (MO.isImplicit())
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return MCOperand();
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return MCOperand::CreateReg(MO.getReg());
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case MachineOperand::MO_Immediate:
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return MCOperand::CreateImm(MO.getImm());
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case MachineOperand::MO_MachineBasicBlock:
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return lowerSymbolOperand(MO, MO.getMBB()->getSymbol(),
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/* MO has no offset field */0);
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case MachineOperand::MO_GlobalAddress:
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return lowerSymbolOperand(MO, Mang->getSymbol(MO.getGlobal()),
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MO.getOffset());
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case MachineOperand::MO_ExternalSymbol: {
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StringRef Name = MO.getSymbolName();
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return lowerSymbolOperand(MO, AsmPrinter.GetExternalSymbolSymbol(Name),
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MO.getOffset());
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}
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case MachineOperand::MO_JumpTableIndex:
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return lowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex()),
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/* MO has no offset field */0);
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case MachineOperand::MO_ConstantPoolIndex:
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return lowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex()),
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MO.getOffset());
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case MachineOperand::MO_BlockAddress: {
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const BlockAddress *BA = MO.getBlockAddress();
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return lowerSymbolOperand(MO, AsmPrinter.GetBlockAddressSymbol(BA),
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MO.getOffset());
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}
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}
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}
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void SystemZMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
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unsigned Opcode = MI->getOpcode();
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// When emitting binary code, start with the shortest form of an instruction
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// and then relax it where necessary.
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if (!AsmPrinter.OutStreamer.hasRawTextSupport())
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Opcode = getShortenedInstr(Opcode);
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OutMI.setOpcode(Opcode);
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for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
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const MachineOperand &MO = MI->getOperand(I);
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MCOperand MCOp = lowerOperand(MO);
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if (MCOp.isValid())
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OutMI.addOperand(MCOp);
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}
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}
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