Chandler Carruth efbbaefea5 [x86] Remove the old vector shuffle lowering code and its flag. ... The new shuffle lowering has been the default for some time. I've enabled the new legality testing by default with no really blocking regressions. I've fuzz tested this very heavily (many millions of fuzz test cases have passed at this point). And this cleans up a ton of code. =] Thanks again to the many folks that helped with this transition. There was a lot of work by others that went into the new shuffle lowering to make it really excellent. In case you aren't using a diff algorithm that can handle this: X86ISelLowering.cpp: 22 insertions(+), 2940 deletions(-) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229964 91177308-0d34-0410-b5e6-96231b3b80d8		2015-02-20 04:25:04 +00:00
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AArch64
ARM	[ARM] Re-re-apply VLD1/VST1 base-update combine.	2015-02-19 23:52:41 +00:00
BPF
CPP
Generic
Hexagon
Inputs
Mips	Revert r229944: EH: Prune unreachable resume instructions during Dwarf EH preparation	2015-02-20 02:15:36 +00:00
MSP430
NVPTX
PowerPC	This patch adds the VSX logical instructions introduced in the Power ISA 2.07. It also removes the added complexity that favors VMX versions of the three instructions.	2015-02-18 16:21:46 +00:00
R600	R600/SI: Add missing offset operand to buffer bothen	2015-02-18 02:04:38 +00:00
SPARC	SelectionDAG: fold (fp_to_u/sint (s/uint_to_fp)) here too	2015-02-16 21:47:58 +00:00
SystemZ	[SystemZ] Support all TLS access models - CodeGen part	2015-02-18 09:13:27 +00:00
Thumb
Thumb2
X86	[x86] Remove the old vector shuffle lowering code and its flag.	2015-02-20 04:25:04 +00:00
XCore	Revert r229944: EH: Prune unreachable resume instructions during Dwarf EH preparation	2015-02-20 02:15:36 +00:00