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https://github.com/c64scene-ar/llvm-6502.git
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38ffffeebc
This patch fixes the multiple breakages on ARM test-suite after the SLP vectorizer was introduced by default on O3. The problem was an illegal vector type on ARMTTI::getCmpSelInstrCost() <3 x i1> which is not simple. The guard protects this code from breaking (cause of the problems) but doesn't fix the issue that is generating the odd vector in the first place, which also needs to be investigated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187658 91177308-0d34-0410-b5e6-96231b3b80d8
76 lines
3.1 KiB
LLVM
76 lines
3.1 KiB
LLVM
; RUN: opt < %s -cost-model -analyze -mtriple=thumbv7-apple-ios6.0.0 -mcpu=swift | FileCheck %s
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target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
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target triple = "thumbv7-apple-ios6.0.0"
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; CHECK: casts
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define void @casts() {
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; Scalar values
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; CHECK: cost of 1 {{.*}} select
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%v1 = select i1 undef, i8 undef, i8 undef
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; CHECK: cost of 1 {{.*}} select
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%v2 = select i1 undef, i16 undef, i16 undef
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; CHECK: cost of 1 {{.*}} select
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%v3 = select i1 undef, i32 undef, i32 undef
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; CHECK: cost of 2 {{.*}} select
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%v4 = select i1 undef, i64 undef, i64 undef
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; CHECK: cost of 1 {{.*}} select
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%v5 = select i1 undef, float undef, float undef
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; CHECK: cost of 1 {{.*}} select
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%v6 = select i1 undef, double undef, double undef
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; Vector values
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; CHECK: cost of 1 {{.*}} select
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%v7 = select <2 x i1> undef, <2 x i8> undef, <2 x i8> undef
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; CHECK: cost of 1 {{.*}} select
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%v8 = select <4 x i1> undef, <4 x i8> undef, <4 x i8> undef
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; CHECK: cost of 1 {{.*}} select
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%v9 = select <8 x i1> undef, <8 x i8> undef, <8 x i8> undef
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; CHECK: cost of 1 {{.*}} select
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%v10 = select <16 x i1> undef, <16 x i8> undef, <16 x i8> undef
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; CHECK: cost of 1 {{.*}} select
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%v11 = select <2 x i1> undef, <2 x i16> undef, <2 x i16> undef
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; CHECK: cost of 1 {{.*}} select
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%v12 = select <4 x i1> undef, <4 x i16> undef, <4 x i16> undef
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; CHECK: cost of 1 {{.*}} select
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%v13 = select <8 x i1> undef, <8 x i16> undef, <8 x i16> undef
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; CHECK: cost of 40 {{.*}} select
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%v13b = select <16 x i1> undef, <16 x i16> undef, <16 x i16> undef
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; CHECK: cost of 1 {{.*}} select
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%v14 = select <2 x i1> undef, <2 x i32> undef, <2 x i32> undef
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; CHECK: cost of 1 {{.*}} select
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%v15 = select <4 x i1> undef, <4 x i32> undef, <4 x i32> undef
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; CHECK: cost of 41 {{.*}} select
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%v15b = select <8 x i1> undef, <8 x i32> undef, <8 x i32> undef
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; CHECK: cost of 82 {{.*}} select
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%v15c = select <16 x i1> undef, <16 x i32> undef, <16 x i32> undef
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; CHECK: cost of 1 {{.*}} select
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%v16 = select <2 x i1> undef, <2 x i64> undef, <2 x i64> undef
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; CHECK: cost of 19 {{.*}} select
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%v16a = select <4 x i1> undef, <4 x i64> undef, <4 x i64> undef
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; CHECK: cost of 50 {{.*}} select
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%v16b = select <8 x i1> undef, <8 x i64> undef, <8 x i64> undef
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; CHECK: cost of 100 {{.*}} select
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%v16c = select <16 x i1> undef, <16 x i64> undef, <16 x i64> undef
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; CHECK: cost of 1 {{.*}} select
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%v17 = select <2 x i1> undef, <2 x float> undef, <2 x float> undef
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; CHECK: cost of 1 {{.*}} select
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%v18 = select <4 x i1> undef, <4 x float> undef, <4 x float> undef
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; CHECK: cost of 1 {{.*}} select
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%v19 = select <2 x i1> undef, <2 x double> undef, <2 x double> undef
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; odd vectors get legalized and should have similar costs
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; CHECK: cost of 1 {{.*}} select
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%v20 = select <1 x i1> undef, <1 x i32> undef, <1 x i32> undef
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; CHECK: cost of 1 {{.*}} select
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%v21 = select <3 x i1> undef, <3 x float> undef, <3 x float> undef
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; CHECK: cost of 4 {{.*}} select
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%v22 = select <5 x i1> undef, <5 x double> undef, <5 x double> undef
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ret void
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}
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