llvm-6502/test/CodeGen/CellSPU/fneg-fabs.ll
Scott Michel c9c8b2a804 CellSPU:
- Rename fcmp.ll test to fcmp32.ll, start adding new double tests to fcmp64.ll
- Fix select_bits.ll test
- Capitulate to the DAGCombiner and move i64 constant loads to instruction
  selection (SPUISelDAGtoDAG.cpp).

  <rant>DAGCombiner will insert all kinds of 64-bit optimizations after
  operation legalization occurs and now we have to do most of the work that
  instruction selection should be doing twice (once to determine if v2i64
  build_vector can be handled by SelectCode(), which then runs all of the
  predicates a second time to select the necessary instructions.) But,
  CellSPU is a good citizen.</rant>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62990 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-26 03:31:40 +00:00

45 lines
1.2 KiB
LLVM

; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: grep fsmbi %t1.s | count 3
; RUN: grep 32768 %t1.s | count 2
; RUN: grep xor %t1.s | count 4
; RUN: grep and %t1.s | count 5
; RUN: grep andbi %t1.s | count 3
target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
target triple = "spu"
define double @fneg_dp(double %X) {
%Y = sub double -0.000000e+00, %X
ret double %Y
}
define <2 x double> @fneg_dp_vec(<2 x double> %X) {
%Y = sub <2 x double> < double -0.0000e+00, double -0.0000e+00 >, %X
ret <2 x double> %Y
}
define float @fneg_sp(float %X) {
%Y = sub float -0.000000e+00, %X
ret float %Y
}
define <4 x float> @fneg_sp_vec(<4 x float> %X) {
%Y = sub <4 x float> <float -0.000000e+00, float -0.000000e+00,
float -0.000000e+00, float -0.000000e+00>, %X
ret <4 x float> %Y
}
declare double @fabs(double)
declare float @fabsf(float)
define double @fabs_dp(double %X) {
%Y = call double @fabs( double %X )
ret double %Y
}
define float @fabs_sp(float %X) {
%Y = call float @fabsf( float %X )
ret float %Y
}