Daniel Sanders 7eedd07d5e [mips] Add backend support for Mips32r[35] and Mips64r[35]. ... Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229695 91177308-0d34-0410-b5e6-96231b3b80d8		2015-02-18 16:24:50 +00:00
..
AArch64	AArch64: Safely handle the incoming sret call argument.	2015-02-16 18:10:47 +00:00
ARM	[ARM] Add missing M/R class CPUs	2015-02-18 10:33:30 +00:00
BPF
CPP
Generic
Hexagon
Inputs
Mips	[mips] Add backend support for Mips32r[35] and Mips64r[35].	2015-02-18 16:24:50 +00:00
MSP430
NVPTX
PowerPC	This patch adds the VSX logical instructions introduced in the Power ISA 2.07. It also removes the added complexity that favors VMX versions of the three instructions.	2015-02-18 16:21:46 +00:00
R600	R600/SI: Add missing offset operand to buffer bothen	2015-02-18 02:04:38 +00:00
SPARC	SelectionDAG: fold (fp_to_u/sint (s/uint_to_fp)) here too	2015-02-16 21:47:58 +00:00
SystemZ	[SystemZ] Support all TLS access models - CodeGen part	2015-02-18 09:13:27 +00:00
Thumb
Thumb2
X86	Fixes two issue in SimplifyDemandedBits of sext_in_reg:	2015-02-18 09:43:40 +00:00
XCore