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https://github.com/c64scene-ar/llvm-6502.git
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29f94c7201
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209577 91177308-0d34-0410-b5e6-96231b3b80d8
199 lines
5.7 KiB
LLVM
199 lines
5.7 KiB
LLVM
; RUN: llc -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s --check-prefix=CHECK
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; First, a simple example from Clang. The registers could plausibly be
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; different, but probably won't be.
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%struct.foo = type { i8, [2 x i8], i8 }
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define [1 x i64] @from_clang([1 x i64] %f.coerce, i32 %n) nounwind readnone {
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; CHECK-LABEL: from_clang:
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; CHECK: bfi {{w[0-9]+}}, {{w[0-9]+}}, #3, #4
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entry:
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%f.coerce.fca.0.extract = extractvalue [1 x i64] %f.coerce, 0
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%tmp.sroa.0.0.extract.trunc = trunc i64 %f.coerce.fca.0.extract to i32
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%bf.value = shl i32 %n, 3
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%0 = and i32 %bf.value, 120
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%f.sroa.0.0.insert.ext.masked = and i32 %tmp.sroa.0.0.extract.trunc, 135
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%1 = or i32 %f.sroa.0.0.insert.ext.masked, %0
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%f.sroa.0.0.extract.trunc = zext i32 %1 to i64
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%tmp1.sroa.1.1.insert.insert = and i64 %f.coerce.fca.0.extract, 4294967040
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%tmp1.sroa.0.0.insert.insert = or i64 %f.sroa.0.0.extract.trunc, %tmp1.sroa.1.1.insert.insert
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%.fca.0.insert = insertvalue [1 x i64] undef, i64 %tmp1.sroa.0.0.insert.insert, 0
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ret [1 x i64] %.fca.0.insert
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}
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define void @test_whole32(i32* %existing, i32* %new) {
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; CHECK-LABEL: test_whole32:
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; CHECK: bfi {{w[0-9]+}}, {{w[0-9]+}}, #26, #5
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%oldval = load volatile i32* %existing
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%oldval_keep = and i32 %oldval, 2214592511 ; =0x83ffffff
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%newval = load volatile i32* %new
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%newval_shifted = shl i32 %newval, 26
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%newval_masked = and i32 %newval_shifted, 2080374784 ; = 0x7c000000
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%combined = or i32 %oldval_keep, %newval_masked
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store volatile i32 %combined, i32* %existing
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ret void
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}
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define void @test_whole64(i64* %existing, i64* %new) {
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; CHECK-LABEL: test_whole64:
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; CHECK: bfi {{x[0-9]+}}, {{x[0-9]+}}, #26, #14
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; CHECK-NOT: and
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; CHECK: ret
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%oldval = load volatile i64* %existing
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%oldval_keep = and i64 %oldval, 18446742974265032703 ; = 0xffffff0003ffffffL
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%newval = load volatile i64* %new
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%newval_shifted = shl i64 %newval, 26
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%newval_masked = and i64 %newval_shifted, 1099444518912 ; = 0xfffc000000
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%combined = or i64 %oldval_keep, %newval_masked
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store volatile i64 %combined, i64* %existing
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ret void
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}
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define void @test_whole32_from64(i64* %existing, i64* %new) {
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; CHECK-LABEL: test_whole32_from64:
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; CHECK: bfxil {{x[0-9]+}}, {{x[0-9]+}}, #0, #16
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; CHECK: ret
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%oldval = load volatile i64* %existing
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%oldval_keep = and i64 %oldval, 4294901760 ; = 0xffff0000
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%newval = load volatile i64* %new
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%newval_masked = and i64 %newval, 65535 ; = 0xffff
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%combined = or i64 %oldval_keep, %newval_masked
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store volatile i64 %combined, i64* %existing
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ret void
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}
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define void @test_32bit_masked(i32 *%existing, i32 *%new) {
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; CHECK-LABEL: test_32bit_masked:
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; CHECK: and
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; CHECK: bfi [[INSERT:w[0-9]+]], {{w[0-9]+}}, #3, #4
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%oldval = load volatile i32* %existing
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%oldval_keep = and i32 %oldval, 135 ; = 0x87
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%newval = load volatile i32* %new
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%newval_shifted = shl i32 %newval, 3
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%newval_masked = and i32 %newval_shifted, 120 ; = 0x78
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%combined = or i32 %oldval_keep, %newval_masked
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store volatile i32 %combined, i32* %existing
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ret void
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}
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define void @test_64bit_masked(i64 *%existing, i64 *%new) {
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; CHECK-LABEL: test_64bit_masked:
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; CHECK: and
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; CHECK: bfi [[INSERT:x[0-9]+]], {{x[0-9]+}}, #40, #8
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%oldval = load volatile i64* %existing
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%oldval_keep = and i64 %oldval, 1095216660480 ; = 0xff_0000_0000
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%newval = load volatile i64* %new
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%newval_shifted = shl i64 %newval, 40
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%newval_masked = and i64 %newval_shifted, 280375465082880 ; = 0xff00_0000_0000
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%combined = or i64 %newval_masked, %oldval_keep
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store volatile i64 %combined, i64* %existing
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ret void
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}
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; Mask is too complicated for literal ANDwwi, make sure other avenues are tried.
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define void @test_32bit_complexmask(i32 *%existing, i32 *%new) {
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; CHECK-LABEL: test_32bit_complexmask:
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; CHECK: and
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; CHECK: bfi {{w[0-9]+}}, {{w[0-9]+}}, #3, #4
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%oldval = load volatile i32* %existing
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%oldval_keep = and i32 %oldval, 647 ; = 0x287
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%newval = load volatile i32* %new
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%newval_shifted = shl i32 %newval, 3
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%newval_masked = and i32 %newval_shifted, 120 ; = 0x278
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%combined = or i32 %oldval_keep, %newval_masked
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store volatile i32 %combined, i32* %existing
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ret void
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}
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; Neither mask is is a contiguous set of 1s. BFI can't be used
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define void @test_32bit_badmask(i32 *%existing, i32 *%new) {
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; CHECK-LABEL: test_32bit_badmask:
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; CHECK-NOT: bfi
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; CHECK-NOT: bfm
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; CHECK: ret
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%oldval = load volatile i32* %existing
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%oldval_keep = and i32 %oldval, 135 ; = 0x87
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%newval = load volatile i32* %new
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%newval_shifted = shl i32 %newval, 3
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%newval_masked = and i32 %newval_shifted, 632 ; = 0x278
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%combined = or i32 %oldval_keep, %newval_masked
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store volatile i32 %combined, i32* %existing
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ret void
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}
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; Ditto
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define void @test_64bit_badmask(i64 *%existing, i64 *%new) {
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; CHECK-LABEL: test_64bit_badmask:
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; CHECK-NOT: bfi
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; CHECK-NOT: bfm
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; CHECK: ret
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%oldval = load volatile i64* %existing
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%oldval_keep = and i64 %oldval, 135 ; = 0x87
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%newval = load volatile i64* %new
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%newval_shifted = shl i64 %newval, 3
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%newval_masked = and i64 %newval_shifted, 664 ; = 0x278
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%combined = or i64 %oldval_keep, %newval_masked
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store volatile i64 %combined, i64* %existing
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ret void
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}
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; Bitfield insert where there's a left-over shr needed at the beginning
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; (e.g. result of str.bf1 = str.bf2)
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define void @test_32bit_with_shr(i32* %existing, i32* %new) {
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; CHECK-LABEL: test_32bit_with_shr:
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%oldval = load volatile i32* %existing
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%oldval_keep = and i32 %oldval, 2214592511 ; =0x83ffffff
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%newval = load i32* %new
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%newval_shifted = shl i32 %newval, 12
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%newval_masked = and i32 %newval_shifted, 2080374784 ; = 0x7c000000
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%combined = or i32 %oldval_keep, %newval_masked
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store volatile i32 %combined, i32* %existing
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; CHECK: lsr [[BIT:w[0-9]+]], {{w[0-9]+}}, #14
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; CHECK: bfi {{w[0-9]+}}, [[BIT]], #26, #5
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ret void
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}
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