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f05522974b
- No intended functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75843 91177308-0d34-0410-b5e6-96231b3b80d8
117 lines
4.5 KiB
C++
117 lines
4.5 KiB
C++
//===-- AlphaTargetMachine.cpp - Define TargetMachine for Alpha -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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#include "Alpha.h"
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#include "AlphaJITInfo.h"
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#include "AlphaTargetAsmInfo.h"
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#include "AlphaTargetMachine.h"
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#include "llvm/Module.h"
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#include "llvm/PassManager.h"
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#include "llvm/Target/TargetMachineRegistry.h"
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#include "llvm/Support/FormattedStream.h"
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using namespace llvm;
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// Register the targets
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extern Target TheAlphaTarget;
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static RegisterTarget<AlphaTargetMachine> X(TheAlphaTarget, "alpha",
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"Alpha [experimental]");
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// Force static initialization.
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extern "C" void LLVMInitializeAlphaTarget() { }
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const TargetAsmInfo *AlphaTargetMachine::createTargetAsmInfo() const {
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return new AlphaTargetAsmInfo(*this);
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}
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AlphaTargetMachine::AlphaTargetMachine(const Target &T, const Module &M,
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const std::string &FS)
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: LLVMTargetMachine(T),
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DataLayout("e-f128:128:128"),
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FrameInfo(TargetFrameInfo::StackGrowsDown, 16, 0),
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JITInfo(*this),
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Subtarget(M, FS),
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TLInfo(*this) {
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setRelocationModel(Reloc::PIC_);
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}
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//===----------------------------------------------------------------------===//
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// Pass Pipeline Configuration
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//===----------------------------------------------------------------------===//
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bool AlphaTargetMachine::addInstSelector(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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PM.add(createAlphaISelDag(*this));
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return false;
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}
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bool AlphaTargetMachine::addPreEmitPass(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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// Must run branch selection immediately preceding the asm printer
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PM.add(createAlphaBranchSelectionPass());
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PM.add(createAlphaLLRPPass(*this));
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return false;
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}
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bool AlphaTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel,
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bool Verbose,
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formatted_raw_ostream &Out) {
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FunctionPass *Printer = getTarget().createAsmPrinter(Out, *this, Verbose);
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if (!Printer)
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llvm_report_error("unable to create assembly printer");
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PM.add(Printer);
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return false;
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}
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bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel,
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bool DumpAsm, MachineCodeEmitter &MCE) {
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PM.add(createAlphaCodeEmitterPass(*this, MCE));
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if (DumpAsm)
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addAssemblyEmitter(PM, OptLevel, true, ferrs());
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return false;
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}
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bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel,
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bool DumpAsm, JITCodeEmitter &JCE) {
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PM.add(createAlphaJITCodeEmitterPass(*this, JCE));
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if (DumpAsm)
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addAssemblyEmitter(PM, OptLevel, true, ferrs());
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return false;
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}
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bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel,
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bool DumpAsm, ObjectCodeEmitter &OCE) {
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PM.add(createAlphaObjectCodeEmitterPass(*this, OCE));
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if (DumpAsm)
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addAssemblyEmitter(PM, OptLevel, true, ferrs());
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return false;
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}
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bool AlphaTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel,
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bool DumpAsm,
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MachineCodeEmitter &MCE) {
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return addCodeEmitter(PM, OptLevel, DumpAsm, MCE);
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}
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bool AlphaTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel,
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bool DumpAsm,
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JITCodeEmitter &JCE) {
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return addCodeEmitter(PM, OptLevel, DumpAsm, JCE);
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}
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bool AlphaTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel,
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bool DumpAsm,
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ObjectCodeEmitter &OCE) {
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return addCodeEmitter(PM, OptLevel, DumpAsm, OCE);
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}
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