Matt Arsenault 0e1619e77c R600: Fix mishandling of load / store chains. ... Fixes various bugs with reordering loads and stores. Scalarized vector loads weren't collecting the chains at all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212473 91177308-0d34-0410-b5e6-96231b3b80d8		2014-07-07 18:34:45 +00:00
..
InstPrinter
MCTargetDesc
TargetInfo
AMDGPU.h	R600/SI: Adjsut SGPR live ranges before register allocation	2014-07-02 20:53:48 +00:00
AMDGPU.td
AMDGPUAsmPrinter.cpp
AMDGPUAsmPrinter.h
AMDGPUCallingConv.td
AMDGPUFrameLowering.cpp
AMDGPUFrameLowering.h
AMDGPUInstrInfo.cpp
AMDGPUInstrInfo.h
AMDGPUInstrInfo.td
AMDGPUInstructions.td
AMDGPUIntrinsicInfo.cpp
AMDGPUIntrinsicInfo.h
AMDGPUIntrinsics.td
AMDGPUISelDAGToDAG.cpp
AMDGPUISelLowering.cpp	R600: Fix mishandling of load / store chains.	2014-07-07 18:34:45 +00:00
AMDGPUISelLowering.h
AMDGPUMachineFunction.cpp
AMDGPUMachineFunction.h
AMDGPUMCInstLower.cpp
AMDGPUMCInstLower.h
AMDGPUPromoteAlloca.cpp
AMDGPURegisterInfo.cpp
AMDGPURegisterInfo.h
AMDGPURegisterInfo.td
AMDGPUSubtarget.cpp
AMDGPUSubtarget.h
AMDGPUTargetMachine.cpp	R600/SI: Adjsut SGPR live ranges before register allocation	2014-07-02 20:53:48 +00:00
AMDGPUTargetMachine.h
AMDGPUTargetTransformInfo.cpp
AMDILCFGStructurizer.cpp
CaymanInstructions.td
CMakeLists.txt	R600/SI: Adjsut SGPR live ranges before register allocation	2014-07-02 20:53:48 +00:00
EvergreenInstructions.td
LLVMBuild.txt
Makefile
Processors.td
R600ClauseMergePass.cpp
R600ControlFlowFinalizer.cpp
R600Defines.h
R600EmitClauseMarkers.cpp
R600ExpandSpecialInstrs.cpp
R600InstrFormats.td
R600InstrInfo.cpp
R600InstrInfo.h
R600Instructions.td
R600Intrinsics.td
R600ISelLowering.cpp	R600: Fix mishandling of load / store chains.	2014-07-07 18:34:45 +00:00
R600ISelLowering.h
R600MachineFunctionInfo.cpp
R600MachineFunctionInfo.h
R600MachineScheduler.cpp
R600MachineScheduler.h
R600OptimizeVectorRegisters.cpp
R600Packetizer.cpp
R600RegisterInfo.cpp
R600RegisterInfo.h
R600RegisterInfo.td
R600Schedule.td
R600TextureIntrinsicsReplacer.cpp
R700Instructions.td
SIAnnotateControlFlow.cpp
SIDefines.h
SIFixSGPRCopies.cpp
SIFixSGPRLiveRanges.cpp	R600/SI: Adjsut SGPR live ranges before register allocation	2014-07-02 20:53:48 +00:00
SIInsertWaits.cpp
SIInstrFormats.td
SIInstrInfo.cpp
SIInstrInfo.h
SIInstrInfo.td	R600/SI: Use a ComplexPattern for ADDR64 addressing of MUBUF loads	2014-07-02 20:53:56 +00:00
SIInstructions.td	R600/SI: Use a ComplexPattern for ADDR64 addressing of MUBUF loads	2014-07-02 20:53:56 +00:00
SIIntrinsics.td
SIISelLowering.cpp	R600: Fix mishandling of load / store chains.	2014-07-07 18:34:45 +00:00
SIISelLowering.h	[codegen,aarch64] Add a target hook to the code generator to control	2014-07-03 00:23:43 +00:00
SILowerControlFlow.cpp
SILowerI1Copies.cpp
SIMachineFunctionInfo.cpp	Fix typo, weird indentation	2014-07-07 18:34:42 +00:00
SIMachineFunctionInfo.h
SIRegisterInfo.cpp
SIRegisterInfo.h
SIRegisterInfo.td
SISchedule.td
SITypeRewriter.cpp	Use cast<> instead of dyn_cast + assert	2014-07-05 21:16:43 +00:00