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0543dab791
Summary:
Two exceptions to this:
test/CodeGen/Mips/octeon.ll
test/CodeGen/Mips/octeon_popcnt.ll
these test extensions to MIPS64
One test is altered for MIPS-IV:
test/CodeGen/Mips/mips64countleading.ll
Tests dclo/dclz which were added in MIPS64. The MIPS-IV version tests
that dclo/dclz are not emitted.
Four tests fail and are not in this patch:
test/CodeGen/Mips/abicalls.ll
test/CodeGen/Mips/fcopysign-f32-f64.ll
test/CodeGen/Mips/fcopysign.ll
test/CodeGen/Mips/stack-alignment.ll
Depends on D3343
Reviewers: matheusalmeida, vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3344
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206185 91177308-0d34-0410-b5e6-96231b3b80d8
39 lines
1.3 KiB
LLVM
39 lines
1.3 KiB
LLVM
; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=32
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; RUN: llc -march=mips64el -mcpu=mips4 -mattr=n64 < %s | \
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; RUN: FileCheck %s -check-prefix=64
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; RUN: llc -march=mips64el -mcpu=mips64 -mattr=n64 < %s | \
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; RUN: FileCheck %s -check-prefix=64
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%struct.S1 = type { [65536 x i8] }
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@s1 = external global %struct.S1
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define void @f() nounwind {
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entry:
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; 32: lui $[[R0:[0-9]+]], 65535
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; 32: addiu $[[R0]], $[[R0]], -24
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; 32: addu $sp, $sp, $[[R0]]
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; 32: lui $[[R1:[0-9]+]], 1
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; 32: addu $[[R1]], $sp, $[[R1]]
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; 32: sw $ra, 20($[[R1]])
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; 64: daddiu $[[R0:[0-9]+]], $zero, 1
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; 64: dsll $[[R0]], $[[R0]], 48
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; 64: daddiu $[[R0]], $[[R0]], -1
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; 64: dsll $[[R0]], $[[R0]], 16
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; 64: daddiu $[[R0]], $[[R0]], -32
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; 64: daddu $sp, $sp, $[[R0]]
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; 64: lui $[[R1:[0-9]+]], 1
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; 64: daddu $[[R1]], $sp, $[[R1]]
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; 64: sd $ra, 24($[[R1]])
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%agg.tmp = alloca %struct.S1, align 1
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%tmp = getelementptr inbounds %struct.S1* %agg.tmp, i32 0, i32 0, i32 0
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call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp, i8* getelementptr inbounds (%struct.S1* @s1, i32 0, i32 0, i32 0), i32 65536, i32 1, i1 false)
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call void @f2(%struct.S1* byval %agg.tmp) nounwind
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ret void
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}
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declare void @f2(%struct.S1* byval)
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declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind
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