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94c002a190
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33749 91177308-0d34-0410-b5e6-96231b3b80d8
56 lines
1.6 KiB
C++
56 lines
1.6 KiB
C++
//===-- llvm/CodeGen/SSARegMap.h --------------------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Map register numbers to register classes that are correctly sized (typed) to
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// hold the information. Assists register allocation. Contained by
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// MachineFunction, should be deleted by register allocator when it is no
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// longer needed.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_SSAREGMAP_H
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#define LLVM_CODEGEN_SSAREGMAP_H
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#include "llvm/Target/MRegisterInfo.h"
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#include "llvm/ADT/IndexedMap.h"
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namespace llvm {
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class TargetRegisterClass;
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class SSARegMap {
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IndexedMap<const TargetRegisterClass*, VirtReg2IndexFunctor> RegClassMap;
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unsigned NextRegNum;
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public:
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SSARegMap() : NextRegNum(MRegisterInfo::FirstVirtualRegister) { }
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const TargetRegisterClass* getRegClass(unsigned Reg) {
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return RegClassMap[Reg];
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}
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/// createVirtualRegister - Create and return a new virtual register in the
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/// function with the specified register class.
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///
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unsigned createVirtualRegister(const TargetRegisterClass *RegClass) {
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assert(RegClass && "Cannot create register without RegClass!");
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RegClassMap.grow(NextRegNum);
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RegClassMap[NextRegNum] = RegClass;
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return NextRegNum++;
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}
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unsigned getLastVirtReg() const {
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return NextRegNum - 1;
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}
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};
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} // End llvm namespace
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#endif
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