mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-04 06:09:05 +00:00
90593d2e1f
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84774 91177308-0d34-0410-b5e6-96231b3b80d8
81 lines
3.3 KiB
C++
81 lines
3.3 KiB
C++
//===- MSP430InstrInfo.h - MSP430 Instruction Information -------*- C++ -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file contains the MSP430 implementation of the TargetInstrInfo class.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#ifndef LLVM_TARGET_MSP430INSTRINFO_H
|
|
#define LLVM_TARGET_MSP430INSTRINFO_H
|
|
|
|
#include "llvm/Target/TargetInstrInfo.h"
|
|
#include "MSP430RegisterInfo.h"
|
|
|
|
namespace llvm {
|
|
|
|
class MSP430TargetMachine;
|
|
|
|
class MSP430InstrInfo : public TargetInstrInfoImpl {
|
|
const MSP430RegisterInfo RI;
|
|
MSP430TargetMachine &TM;
|
|
public:
|
|
explicit MSP430InstrInfo(MSP430TargetMachine &TM);
|
|
|
|
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
|
|
/// such, whenever a client has an instance of instruction info, it should
|
|
/// always be able to get register info as well (through this method).
|
|
///
|
|
virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
|
|
|
|
bool copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
|
unsigned DestReg, unsigned SrcReg,
|
|
const TargetRegisterClass *DestRC,
|
|
const TargetRegisterClass *SrcRC) const;
|
|
|
|
bool isMoveInstr(const MachineInstr& MI,
|
|
unsigned &SrcReg, unsigned &DstReg,
|
|
unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
|
|
|
|
virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI,
|
|
unsigned SrcReg, bool isKill,
|
|
int FrameIndex,
|
|
const TargetRegisterClass *RC) const;
|
|
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI,
|
|
unsigned DestReg, int FrameIdx,
|
|
const TargetRegisterClass *RC) const;
|
|
|
|
virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI,
|
|
const std::vector<CalleeSavedInfo> &CSI) const;
|
|
virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI,
|
|
const std::vector<CalleeSavedInfo> &CSI) const;
|
|
|
|
// Branch folding goodness
|
|
bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
|
|
bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
|
|
bool isUnpredicatedTerminator(const MachineInstr *MI) const;
|
|
bool AnalyzeBranch(MachineBasicBlock &MBB,
|
|
MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
|
|
SmallVectorImpl<MachineOperand> &Cond,
|
|
bool AllowModify) const;
|
|
|
|
unsigned RemoveBranch(MachineBasicBlock &MBB) const;
|
|
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
|
MachineBasicBlock *FBB,
|
|
const SmallVectorImpl<MachineOperand> &Cond) const;
|
|
|
|
};
|
|
|
|
}
|
|
|
|
#endif
|