mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-02-07 14:33:15 +00:00
442f620296
Add a pass AArch64InterleavedAccess to identify and match interleaved memory accesses. This pass transforms an interleaved load/store into ldN/stN intrinsic. As Loop Vectorizor disables optimization on interleaved accesses by default, this optimization is also disabled by default. To enable it by "-aarch64-interleaved-access-opt=true"
E.g. Transform an interleaved load (Factor = 2):
%wide.vec = load <8 x i32>, <8 x i32>* %ptr
%v0 = shuffle %wide.vec, undef, <0, 2, 4, 6> ; Extract even elements
%v1 = shuffle %wide.vec, undef, <1, 3, 5, 7> ; Extract odd elements
Into:
%ld2 = { <4 x i32>, <4 x i32> } call aarch64.neon.ld2(%ptr)
%v0 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 0
%v1 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 1
E.g. Transform an interleaved store (Factor = 2):
%i.vec = shuffle %v0, %v1, <0, 4, 1, 5, 2, 6, 3, 7> ; Interleaved vec
store <8 x i32> %i.vec, <8 x i32>* %ptr
Into:
%v0 = shuffle %i.vec, undef, <0, 1, 2, 3>
%v1 = shuffle %i.vec, undef, <4, 5, 6, 7>
call void aarch64.neon.st2(%v0, %v1, %ptr)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239514 91177308-0d34-0410-b5e6-96231b3b80d8
57 lines
1.9 KiB
CMake
57 lines
1.9 KiB
CMake
set(LLVM_TARGET_DEFINITIONS AArch64.td)
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tablegen(LLVM AArch64GenRegisterInfo.inc -gen-register-info)
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tablegen(LLVM AArch64GenInstrInfo.inc -gen-instr-info)
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tablegen(LLVM AArch64GenMCCodeEmitter.inc -gen-emitter)
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tablegen(LLVM AArch64GenMCPseudoLowering.inc -gen-pseudo-lowering)
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tablegen(LLVM AArch64GenAsmWriter.inc -gen-asm-writer)
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tablegen(LLVM AArch64GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1)
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tablegen(LLVM AArch64GenAsmMatcher.inc -gen-asm-matcher)
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tablegen(LLVM AArch64GenDAGISel.inc -gen-dag-isel)
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tablegen(LLVM AArch64GenFastISel.inc -gen-fast-isel)
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tablegen(LLVM AArch64GenCallingConv.inc -gen-callingconv)
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tablegen(LLVM AArch64GenSubtargetInfo.inc -gen-subtarget)
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tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler)
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add_public_tablegen_target(AArch64CommonTableGen)
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add_llvm_target(AArch64CodeGen
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AArch64A57FPLoadBalancing.cpp
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AArch64AddressTypePromotion.cpp
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AArch64AdvSIMDScalarPass.cpp
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AArch64AsmPrinter.cpp
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AArch64BranchRelaxation.cpp
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AArch64CleanupLocalDynamicTLSPass.cpp
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AArch64CollectLOH.cpp
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AArch64ConditionalCompares.cpp
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AArch64DeadRegisterDefinitionsPass.cpp
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AArch64ExpandPseudoInsts.cpp
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AArch64FastISel.cpp
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AArch64A53Fix835769.cpp
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AArch64FrameLowering.cpp
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AArch64ConditionOptimizer.cpp
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AArch64ISelDAGToDAG.cpp
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AArch64ISelLowering.cpp
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AArch64InstrInfo.cpp
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AArch64LoadStoreOptimizer.cpp
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AArch64MCInstLower.cpp
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AArch64PromoteConstant.cpp
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AArch64PBQPRegAlloc.cpp
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AArch64RegisterInfo.cpp
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AArch64SelectionDAGInfo.cpp
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AArch64InterleavedAccess.cpp
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AArch64StorePairSuppress.cpp
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AArch64Subtarget.cpp
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AArch64TargetMachine.cpp
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AArch64TargetObjectFile.cpp
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AArch64TargetTransformInfo.cpp
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)
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add_dependencies(LLVMAArch64CodeGen intrinsics_gen)
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add_subdirectory(TargetInfo)
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add_subdirectory(AsmParser)
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add_subdirectory(Disassembler)
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add_subdirectory(InstPrinter)
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add_subdirectory(MCTargetDesc)
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add_subdirectory(Utils)
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