mirror of
https://github.com/c64scene-ar/llvm-6502.git
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29f94c7201
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209577 91177308-0d34-0410-b5e6-96231b3b80d8
116 lines
3.7 KiB
LLVM
116 lines
3.7 KiB
LLVM
; RUN: llc -mtriple=arm64-linux-gnu -o - %s -mcpu=cyclone | FileCheck %s
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; RUN: llc -mtriple=arm64-linux-gnu -o - %s -O0 -mcpu=cyclone | FileCheck %s --check-prefix=CHECK-FAST
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; RUN: llc -mtriple=arm64-linux-gnu -relocation-model=pic -o - %s -mcpu=cyclone | FileCheck %s --check-prefix=CHECK-PIC
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; RUN: llc -mtriple=arm64-linux-gnu -O0 -relocation-model=pic -o - %s -mcpu=cyclone | FileCheck %s --check-prefix=CHECK-FAST-PIC
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@var8 = external global i8, align 1
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@var16 = external global i16, align 2
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@var32 = external global i32, align 4
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@var64 = external global i64, align 8
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define i8 @test_i8(i8 %new) {
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%val = load i8* @var8, align 1
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store i8 %new, i8* @var8
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ret i8 %val
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; CHECK-LABEL: test_i8:
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; CHECK: adrp x[[HIREG:[0-9]+]], var8
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; CHECK: ldrb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8]
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; CHECK: strb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8]
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; CHECK-PIC-LABEL: test_i8:
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; CHECK-PIC: adrp x[[HIREG:[0-9]+]], :got:var8
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; CHECK-PIC: ldr x[[VAR_ADDR:[0-9]+]], [x[[HIREG]], :got_lo12:var8]
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; CHECK-PIC: ldrb {{w[0-9]+}}, [x[[VAR_ADDR]]]
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; CHECK-FAST: adrp x[[HIREG:[0-9]+]], var8
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; CHECK-FAST: ldrb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8]
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; CHECK-FAST-PIC: adrp x[[HIREG:[0-9]+]], :got:var8
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; CHECK-FAST-PIC: ldr x[[VARADDR:[0-9]+]], [x[[HIREG]], :got_lo12:var8]
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; CHECK-FAST-PIC: ldr {{w[0-9]+}}, [x[[VARADDR]]]
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}
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define i16 @test_i16(i16 %new) {
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%val = load i16* @var16, align 2
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store i16 %new, i16* @var16
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ret i16 %val
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; CHECK-LABEL: test_i16:
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; CHECK: adrp x[[HIREG:[0-9]+]], var16
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; CHECK: ldrh {{w[0-9]+}}, [x[[HIREG]], :lo12:var16]
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; CHECK: strh {{w[0-9]+}}, [x[[HIREG]], :lo12:var16]
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; CHECK-FAST: adrp x[[HIREG:[0-9]+]], var16
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; CHECK-FAST: ldrh {{w[0-9]+}}, [x[[HIREG]], :lo12:var16]
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}
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define i32 @test_i32(i32 %new) {
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%val = load i32* @var32, align 4
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store i32 %new, i32* @var32
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ret i32 %val
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; CHECK-LABEL: test_i32:
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; CHECK: adrp x[[HIREG:[0-9]+]], var32
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; CHECK: ldr {{w[0-9]+}}, [x[[HIREG]], :lo12:var32]
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; CHECK: str {{w[0-9]+}}, [x[[HIREG]], :lo12:var32]
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; CHECK-FAST: adrp x[[HIREG:[0-9]+]], var32
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; CHECK-FAST: add {{x[0-9]+}}, x[[HIREG]], :lo12:var32
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}
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define i64 @test_i64(i64 %new) {
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%val = load i64* @var64, align 8
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store i64 %new, i64* @var64
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ret i64 %val
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; CHECK-LABEL: test_i64:
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; CHECK: adrp x[[HIREG:[0-9]+]], var64
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; CHECK: ldr {{x[0-9]+}}, [x[[HIREG]], :lo12:var64]
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; CHECK: str {{x[0-9]+}}, [x[[HIREG]], :lo12:var64]
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; CHECK-FAST: adrp x[[HIREG:[0-9]+]], var64
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; CHECK-FAST: add {{x[0-9]+}}, x[[HIREG]], :lo12:var64
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}
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define i64* @test_addr() {
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ret i64* @var64
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; CHECK-LABEL: test_addr:
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; CHECK: adrp [[HIREG:x[0-9]+]], var64
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; CHECK: add x0, [[HIREG]], :lo12:var64
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; CHECK-FAST: adrp [[HIREG:x[0-9]+]], var64
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; CHECK-FAST: add x0, [[HIREG]], :lo12:var64
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}
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@hiddenvar = hidden global i32 0, align 4
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@protectedvar = protected global i32 0, align 4
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define i32 @test_vis() {
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%lhs = load i32* @hiddenvar, align 4
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%rhs = load i32* @protectedvar, align 4
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%ret = add i32 %lhs, %rhs
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ret i32 %ret
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; CHECK-PIC: adrp {{x[0-9]+}}, hiddenvar
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; CHECK-PIC: ldr {{w[0-9]+}}, [{{x[0-9]+}}, :lo12:hiddenvar]
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; CHECK-PIC: adrp {{x[0-9]+}}, protectedvar
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; CHECK-PIC: ldr {{w[0-9]+}}, [{{x[0-9]+}}, :lo12:protectedvar]
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}
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@var_default = external global [2 x i32]
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define i32 @test_default_align() {
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%addr = getelementptr [2 x i32]* @var_default, i32 0, i32 0
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%val = load i32* %addr
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ret i32 %val
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; CHECK-LABEL: test_default_align:
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; CHECK: adrp x[[HIREG:[0-9]+]], var_default
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; CHECK: ldr w0, [x[[HIREG]], :lo12:var_default]
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}
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define i64 @test_default_unaligned() {
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%addr = bitcast [2 x i32]* @var_default to i64*
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%val = load i64* %addr
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ret i64 %val
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; CHECK-LABEL: test_default_unaligned:
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; CHECK: adrp [[HIREG:x[0-9]+]], var_default
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; CHECK: add x[[ADDR:[0-9]+]], [[HIREG]], :lo12:var_default
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; CHECK: ldr x0, [x[[ADDR]]]
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}
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