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https://github.com/c64scene-ar/llvm-6502.git
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f103b3d1b9
detect a pattern which can be implemented with a small 'shl' embedded in the addressing mode scale. This happens in real code as follows: unsigned x = my_accelerator_table[input >> 11]; Here we have some lookup table that we look into using the high bits of 'input'. Each entity in the table is 4-bytes, which means this implicitly gets turned into (once lowered out of a GEP): *(unsigned*)((char*)my_accelerator_table + ((input >> 11) << 2)); The shift right followed by a shift left is canonicalized to a smaller shift right and masking off the low bits. That hides the shift right which x86 has an addressing mode designed to support. We now detect masks of this form, and produce the longer shift right followed by the proper addressing mode. In addition to saving a (rather large) instruction, this also reduces stalls in Intel chips on benchmarks I've measured. In order for all of this to work, one part of the DAG needs to be canonicalized *still further* than it currently is. This involves removing pointless 'trunc' nodes between a zextload and a zext. Without that, we end up generating spurious masks and hiding the pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147936 91177308-0d34-0410-b5e6-96231b3b80d8
78 lines
2.0 KiB
LLVM
78 lines
2.0 KiB
LLVM
; RUN: llc < %s -march=x86 | FileCheck %s
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define i32 @t1(i8* %X, i32 %i) {
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; CHECK: t1:
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; CHECK-NOT: and
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; CHECK: movzbl
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; CHECK: movl (%{{...}},%{{...}},4),
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; CHECK: ret
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entry:
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%tmp2 = shl i32 %i, 2
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%tmp4 = and i32 %tmp2, 1020
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%tmp7 = getelementptr i8* %X, i32 %tmp4
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%tmp78 = bitcast i8* %tmp7 to i32*
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%tmp9 = load i32* %tmp78
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ret i32 %tmp9
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}
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define i32 @t2(i16* %X, i32 %i) {
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; CHECK: t2:
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; CHECK-NOT: and
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; CHECK: movzwl
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; CHECK: movl (%{{...}},%{{...}},4),
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; CHECK: ret
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entry:
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%tmp2 = shl i32 %i, 1
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%tmp4 = and i32 %tmp2, 131070
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%tmp7 = getelementptr i16* %X, i32 %tmp4
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%tmp78 = bitcast i16* %tmp7 to i32*
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%tmp9 = load i32* %tmp78
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ret i32 %tmp9
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}
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define i32 @t3(i16* %i.ptr, i32* %arr) {
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; This case is tricky. The lshr followed by a gep will produce a lshr followed
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; by an and to remove the low bits. This can be simplified by doing the lshr by
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; a greater constant and using the addressing mode to scale the result back up.
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; To make matters worse, because of the two-phase zext of %i and their reuse in
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; the function, the DAG can get confusing trying to re-use both of them and
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; prevent easy analysis of the mask in order to match this.
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; CHECK: t3:
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; CHECK-NOT: and
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; CHECK: shrl
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; CHECK: addl (%{{...}},%{{...}},4),
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; CHECK: ret
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entry:
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%i = load i16* %i.ptr
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%i.zext = zext i16 %i to i32
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%index = lshr i32 %i.zext, 11
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%val.ptr = getelementptr inbounds i32* %arr, i32 %index
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%val = load i32* %val.ptr
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%sum = add i32 %val, %i.zext
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ret i32 %sum
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}
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define i32 @t4(i16* %i.ptr, i32* %arr) {
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; A version of @t3 that has more zero extends and more re-use of intermediate
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; values. This exercise slightly different bits of canonicalization.
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; CHECK: t4:
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; CHECK-NOT: and
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; CHECK: shrl
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; CHECK: addl (%{{...}},%{{...}},4),
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; CHECK: ret
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entry:
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%i = load i16* %i.ptr
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%i.zext = zext i16 %i to i32
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%index = lshr i32 %i.zext, 11
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%index.zext = zext i32 %index to i64
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%val.ptr = getelementptr inbounds i32* %arr, i64 %index.zext
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%val = load i32* %val.ptr
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%sum.1 = add i32 %val, %i.zext
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%sum.2 = add i32 %sum.1, %index
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ret i32 %sum.2
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}
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