mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-04 09:30:13 +00:00
769ea2f93f
This patch will optimize the following cases on X86 (a > b) ? (a-b) : 0 (a >= b) ? (a-b) : 0 (b < a) ? (a-b) : 0 (b <= a) ? (a-b) : 0 FROM movl %edi, %ecx subl %esi, %ecx cmpl %edi, %esi movl $0, %eax cmovll %ecx, %eax TO xorl %eax, %eax subl %esi, %edi cmovll %eax, %edi movl %edi, %eax rdar: 10734411 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155919 91177308-0d34-0410-b5e6-96231b3b80d8
77 lines
1.6 KiB
LLVM
77 lines
1.6 KiB
LLVM
; RUN: llc < %s -march=x86 -mcpu=pentiumpro | FileCheck %s
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define i32 @f(i32 %X) {
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entry:
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; CHECK: f:
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; CHECK: jns
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%tmp1 = add i32 %X, 1 ; <i32> [#uses=1]
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%tmp = icmp slt i32 %tmp1, 0 ; <i1> [#uses=1]
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br i1 %tmp, label %cond_true, label %cond_next
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cond_true: ; preds = %entry
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%tmp2 = tail call i32 (...)* @bar( ) ; <i32> [#uses=0]
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br label %cond_next
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cond_next: ; preds = %cond_true, %entry
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%tmp3 = tail call i32 (...)* @baz( ) ; <i32> [#uses=0]
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ret i32 undef
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}
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declare i32 @bar(...)
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declare i32 @baz(...)
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; rdar://10633221
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define i32 @g(i32 %a, i32 %b) nounwind {
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entry:
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; CHECK: g:
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; CHECK-NOT: test
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; CHECK: cmovs
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%sub = sub nsw i32 %a, %b
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%cmp = icmp sgt i32 %sub, 0
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%cond = select i1 %cmp, i32 %sub, i32 0
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ret i32 %cond
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}
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; rdar://10734411
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define i32 @h(i32 %a, i32 %b) nounwind {
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entry:
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; CHECK: h:
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; CHECK-NOT: cmp
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; CHECK: cmov
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%cmp = icmp slt i32 %b, %a
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%sub = sub nsw i32 %a, %b
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%cond = select i1 %cmp, i32 %sub, i32 0
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ret i32 %cond
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}
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define i32 @i(i32 %a, i32 %b) nounwind {
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entry:
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; CHECK: i:
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; CHECK-NOT: cmp
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; CHECK: cmov
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%cmp = icmp sgt i32 %a, %b
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%sub = sub nsw i32 %a, %b
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%cond = select i1 %cmp, i32 %sub, i32 0
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ret i32 %cond
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}
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define i32 @j(i32 %a, i32 %b) nounwind {
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entry:
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; CHECK: j:
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; CHECK-NOT: cmp
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; CHECK: cmov
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%cmp = icmp ugt i32 %a, %b
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%sub = sub i32 %a, %b
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%cond = select i1 %cmp, i32 %sub, i32 0
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ret i32 %cond
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}
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define i32 @k(i32 %a, i32 %b) nounwind {
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entry:
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; CHECK: k:
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; CHECK-NOT: cmp
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; CHECK: cmov
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%cmp = icmp ult i32 %b, %a
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%sub = sub i32 %a, %b
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%cond = select i1 %cmp, i32 %sub, i32 0
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ret i32 %cond
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}
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